High speed CMOS imager column CDS circuit

• US 6,421,085 B1
• Filed: 04/14/1998
• Issued: 07/16/2002
• Est. Priority Date: 04/14/1998
• Status: Expired due to Term

• Current Assignee: Omnivision Technologies Incorporated (Will Semiconductor Co., Ltd. Shanghai)
• Original Assignee: Eastman Kodak Company
• Inventors: Xu, Weize
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Villecco, John M.
• Application Number:
  US09/059,814
• Time in Patent Office: 1,554 Days
• Field of Search: 348/302, 348/303, 348/304, 348/305, 348/306, 348/307, 348/308, 348/309, 348/310
• US Class Current: 348/308
• CPC Class Codes: H04N 25/616 involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
• CPC Class Codes: H04N 25/677 for reducing the column or line fixed pattern noise
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

A correlated double sampling unit within a CMOS imager employs an image sensor having a plurality of photodetectors arranged in a series of rows and columns with a row addressing circuit, a column addressing circuit, a first sample and hold circuit allocated for each of the columns, a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns, and a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits.

Claims

1. A CMOS imager having a correlated double sampling unit comprising:

an image sensor having a plurality of photodetectors arranged in a series of rows and columns;

a row addressing circuit;

a column addressing circuit;

a first sample and hold circuit allocated for each of the columns;

a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns;

a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits;

a linear gain amplifier contained in each of the first sample and hold circuits; and

an enabling circuit that enables the linear gain amplifiers for the column that is currently being readout and the column that is to be readout after the column currently being readout;

wherein the enabling circuit enables the linear gain amplifier for the column to be read next after the column that is currently being read to precharge conductive lines connecting the second sample and hold circuit to the first sample and hold circuit within the column to be read out next.

2. The correlated double sampling unit of claim 1 further comprising an output driver configured to a selection circuit which will output from only one of the second sampling circuits.

3. The correlated double sampling unit of claim 1 wherein only one of the columns is being readout at a given time.

4. The correlated double sampling circuit of claim 1 wherein there are two second sample and hold circuits, each of the second sample and hold circuits are associated with, essentially, half of the first sample and hold circuits.

5. The correlated double sampling circuit of claim 4 wherein the two second sample and hold circuits are arranged such that each of the second sample and hold circuits are associated with alternating columns.

6. The correlated double sampling circuit of claim 1 further comprising a precharge circuit that precharges the second sample and hold circuit.

7. The correlated double sampling circuit of claim 6 further comprising a readout circuit that reads charge stored within the second clamping circuit concurrently with the precharge circuit placing charge within the second sample and hold circuit.

8. A method of making a CMOS imager having a correlated double sampling unit comprising:

providing a CMOS image sensor having a plurality of photodetectors arranged in a series of rows and columns with a row addressing circuit for addressing the rows, a column addressing circuit for addressing the columns, a first sample and hold circuit allocated for each of the columns and a transfer circuit operatively connecting each of the columns to the first sample and hold circuit for each of the columns;

additionally providing a plurality of second sample and hold circuits, each of the second sample and hold circuits being operatively connected to a subset of the first sample and hold circuits;

providing a linear gain amplifier contained within each of the first sample and hold circuits; and

providing an enabling circuit that enables the linear gain amplifiers for the column that is currently being readout as well as the column that is to be readout after the column that is currently being readout and providing the enabling circuit such that it enables the linear gain amplifier for the column to be read after the column that is currently being read to precharge conductive lines connecting the second sample and hold circuit to the first sample and hold circuit within the column to be read out next.

9. The method of claim 8 wherein the step of additionally providing further comprises providing an output driver configured to a selection circuit such that the output driver is operatively connected to only one of the second sampling circuits at a given time.

10. The method of claim 8 wherein the step of additionally providing further comprises means for reading out only one of the columns at a given time.

11. The method of claim 8 wherein the additionally providing step further comprises providing second sampling circuit such that there are two second sample and hold circuits, and each of the second sample and hold circuits are associated with, essentially, half of the first sample and hold circuits.

12. The method of claim 11 wherein the additionally providing step further comprises providing the two second sample and hold circuits such that they are arranged with each of the second sample and hold circuits being associated with alternating columns.

13. The method of claim 8 wherein the providing step further comprises a precharge circuit that precharges the second sample and hold circuit.

14. The method of claim 13 wherein the providing step further comprises providing a readout circuit that reads charge stored within the second clamping circuit concurrently with the precharge circuit placing charge within the second sample and hold circuit.