Baseband signal converter for a wideband impulse radio receiver

• US 6,421,389 B1
• Filed: 07/16/1999
• Issued: 07/16/2002
• Est. Priority Date: 07/16/1999
• Status: Expired due to Term

• Current Assignee: Humatics Corporation
• Original Assignee: Time Domain Corporation (Humatics Corporation)
• Inventors: Rowe, David A., Pollack, Bret A., Larson, Lawrence E., Jett, Preston
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): HA, DAC V
• Application Number:
  US09/356,384
• Time in Patent Office: 1,096 Days
• Field of Search: 375/316, 375/340, 375/342, 375/343, 375/349, 375/355, 375/256
• US Class Current: 375/256
• CPC Class Codes: H04B 1/71637 Receiver aspects H04B1/7183 takes precedence
• CPC Class Codes: H04B 1/7183 Synchronisation
• CPC Class Codes: H04B 1/719 Interference-related aspects
• CPC Class Codes: H04L 25/4902 Pulse width modulation; Pulse position modulation

Abstract

A baseband signal converter device for an impulse radio receiver combines multiple converter circuits and an RF amplifier in a single integrated circuit package. Each converter circuit includes an integrator circuit that integrates a portion of each RF pulse during a sampling period triggered by a timing pulse generator. The integrator capacitor is isolated by a pair of Schottky diodes connected to a pair of load resistors. A current equalizer circuit equalizes the current flowing through the load resistors when the integrator is not sampling. Current steering logic transfers load current between the diodes and a constant bias circuit depending on whether a sampling pulse is present.

Claims

1. A device for converting RF pulses received by a wideband impulse radio receiver into one or more baseband signals, the device comprising:

a. an RF input for receiving the RF pulses;

b. multiple timing inputs for receiving separate timing signals;

c. multiple converter circuits, the converter circuits each having a signal input electrically coupled in parallel to the RF input;

d. each converter circuit having a second input electrically coupled to one of the timing inputs such that each converter circuit can receive one of the separate timing signals;

e. each converter circuit having a baseband signal output;

f. the device is packaged as a single integrated circuit in which the converter circuits are arranged on a common substrate for single or concurrent operation;

g. wherein each converter circuit includes a signal integrator that is responsive to one of the separate timing signals and that integrates the RF pulses to provide a converter output signal coupled to a corresponding one of the baseband signal outputs; and

h. wherein each signal integrator comprises a capacitor having first and second capacitor terminals electrically connected to the signal input, and wherein the RF pulses are provided to the signal integrator as a differential signal applied across the first and second capacitor terminals.

2. The device of claim 1, each signal integrator further comprising a first resistive load electrically coupled to the first capacitor terminal and a second resistive load electrically coupled to the second capacitor terminal.

3. The device of claim 2 wherein the differential signal is generated by a primary current source operable to charge and discharge the capacitor through the first and second resistive loads in response to reception of the RF pulses and in response to the timing pulses, and the signal integrator further comprises a current equalizer operable to equalize average current flow through the first and second resistive loads.

4. The device of claim 3 wherein each signal integrator further comprises a first diode connected in series between the first resistive load and the first capacitor terminal and a second diode connected in series between the second resistive load and the second capacitor terminal.

5. The device of claim 4 wherein the first and second diodes are Schottky diodes.

6. The device of claim 5, each signal integrator further comprising a first auxiliary current source electrically connected to the first capacitor terminal and a second auxiliary current source electrically connected to the second capacitor terminal.

7. The device of claim 6 wherein the primary current source includes current steering logic operable to steer load current through the load resistors such that the load current passes continuously through the first and second load resistors but passes through the first and second diodes only when a sampling pulse is applied to the signal integrator.

8. The device of claim 5 wherein each converter circuit further comprises:

a. a track and hold control circuit electrically connected to the timing input and responsive to the timing signals to generate track and hold timing pulses; and

b. a track and hold circuit operably connected to the track and hold control circuit responsive to the track and hold timing pulses and to a value of the converter output signal to track the value of the converter output signal for a tracking period and to hold the value of the converter output signal for hold period that exceeds the tracking period.

9. The device of claim 8 wherein the timing pulses have pulse positions that vary in accordance with a receiver time offset code, the receiver time offset code corresponding to a transmitter time offset code that varies the time positions of the RF pulses.

10. A device for converting wideband radio signals into baseband signals, the wideband radio signals comprising multiple RF pulses having an RF pulse period, the device comprising:

a. a wideband RF input adapted to receive the radio signals;

b. a timing input operable to receive primary timing pulses;

c. a pulse generator electrically connected to the timing input and operable to generate sampling pulses at a pulse generator output in response to the primary timing pulses received at the timing input,

d. a converter circuit having a signal input operably connected to the RF input, and a timing pulse input operably connected to the pulse generator output, the converter circuit including a signal integrator that is responsive to the sampling pulses and that integrates the RF pulses to provide a converter output signal across positive and negative converter output terminals; and

e. the signal integrator comprising a capacitor having first and second capacitor terminals electrically connected across the converter output terminals, and wherein the radio signals are provided to the signal integrator as a differential signal applied across the first and second capacitor terminals.

11. The device of claim 10, the signal integrator further comprising a first resistive load electrically coupled to the first capacitor terminal and a second resistive load electrically coupled to the second capacitor terminal.

12. The device of claim 11 wherein the differential signal is generated by a primary current source operable to charge and discharge the capacitor through the first and second resistive loads in response to reception of the monocycle pulses and in response to the sampling pulses, and the signal integrator further comprises a current equalizer operable to equalize average current flow through the first and second resistive loads.

13. The device of claim 12 wherein the signal integrator further comprises a first diode connected in series between the first resistive load and the first capacitor terminal and a second diode connected in series between the second resistive load and the second capacitor terminal.

14. The device of claim 13 wherein the first and second diodes are Schottky diodes.

15. The device of claim 12 further comprising a first auxiliary current source electrically connected to the first capacitor terminal and a second auxiliary current source electrically connected to the second capacitor terminal.

16. The device of claim 15 wherein the primary current source includes current steering logic operable to steer load current through the load resistors such that the load current passes continuously through the first and load resistors but passes through the first and second diodes only when a sampling pulse is applied to the signal integrator.

17. The device of claim 10, the sampling pulses having a pulse width that is less than the RF pulse period.

18. The device of claim 10 wherein each primary timing pulse has a known pulse width that exceeds the RF pulse period.

19. The device of claim 10 further comprising:

a. a track and hold control circuit electrically connected to the timing input and responsive to the primary timing pulses to generate track and hold timing pulses, the track and hold timing pulses having a pulse width that is greater than the width of the sampling pulses and shorter than the width of the primary timing pulses, the width of the track and hold timing pulses defining a tracking period; and

b. a track and hold circuit operably connected to the track and hold control circuit and to the converter output terminals, the track and hold circuit responsive to the track and hold timing pulses and to a value of the converter output signal, the track and hold circuit operable to track the value of the converter output signal during the tracking period and hold at a device output a device output signal that is at least a portion of the value of the converter output signal for a hold period that exceeds the tracking period.

20. The device of claim 19 wherein the primary timing pulses have pulse positions that vary in accordance with a receiver time offset code, the receiver time offset code corresponding to a transmitter time offset code that varies the time positions of the RF pulses.

21. A method of converting RF impulses into a baseband signal in a wideband impulse radio receiver comprising the steps of:

a. generating a sampling pulse to define a sampling period and a non-sampling period;

b. applying the RF impulses across an integrating capacitor in a signal integrator circuit to provide an output voltage; and

c. isolating the integrating capacitor from the rest of the integrator circuit during the non-sampling period.

22. The method of claim 21 wherein the RF impulses are applied across the integrating capacitor as a differential signal.

23. The method of claim 22 wherein the step of isolating the integrating capacitor is performed by switching a pair of diodes connected to the integrating capacitor from a low impedance state to a high impedance state in response to the sampling pulses.

24. The method of claim 23 further comprising the step of determining the baseband signal as a function of an output voltage generated by load currents through first and second resistive loads connected to the integrating capacitor.

25. The method of claim 24 further comprising the step of equalizing the load currents in the first and second resistive loads.

26. The method of claim 21 further comprising the steps of tracking the output voltage for a tracking period and holding the output voltage for a hold period to provide the baseband signal.

27. A device for converting RF impulses into a baseband signal comprising:

a. timing generator means for generating sampling pulses in response to a primary timing signal, the sampling pulses defining sampling and non-sampling periods;

b. integrator means operably connected to the timing generator means and to a device RF input to integrate RF pulses present at the RF input during the sampling periods to provide an integrator output signal;

c. track and hold means to track and hold the integrator output signal for a track and hold period that exceeds the sampling period to provide the baseband signal, the track and hold means having an input operably connected to the integrator means; and

d. wherein the RF pulses are provided to the integrator means as differential signals.

28. The device of claim 27 wherein the sampling pulses are provided to the integrator means as differential signals.

29. The device of claim 27 wherein the integrator means comprises a capacitor having first and second capacitor terminals coupled to corresponding first and second load means and wherein the integrator output signal is generated by first and second load currents passing through the first and second load means.

30. The device of claim 29 further comprising isolation means for electrically isolating the capacitor from the first and second load means during the non-sampling periods.

31. The device of claim 30 wherein the isolation means comprises a first diode coupling the first capacitor terminal to the first load means and a second diode coupling the second capacitor terminal to the second load means.

32. The device of claim 31 wherein the isolation means further comprises switching means for switching the first and second diodes between a low impedance state and a high impedance state.

33. The device of claim 32 wherein the switching means comprises a first current assist circuit electrically connected across the first diode and a second current assist circuit electrically connected across the second diode, the first and second current assist circuits responsive to the sampling pulses.

34. The device of claim 29 further comprising current equalizer means for automatically equalizing the first and second load currents.

35. The device of claim 29 wherein the first load means includes a first load resistor connected between a supply voltage and the first capacitor terminal and the second load means includes a second load resistor connected between the supply voltage and the second capacitor terminal.

36. The device of claim 35 further comprising current steering logic means coupled to the first and second load resistors for maintaining a continuous flow of load current through the first and second load resistors during the sampling and non-sampling periods.

37. The device of claim 36 wherein the current steering logic means includes a constant bias circuit.

38. The device of claim 36 further comprising means to reset the integrator output signal.

39. A method of integrating a pulse signal in a wideband impulse radio to provide an integrator output signal comprising the steps of:

a. using the pulse signal to charge an integrator capacitor;

b. isolating the integrator capacitor by switching diodes in circuit with the integrator capacitor from a low impedance state to a high impedance state; and

c. measuring the charge in the integrator capacitor to obtain the integrator output signal.

40. The method of claim 39 further comprising the step of tracking and holding the integrator output signal at the end of the pulse signal for a track and hold period.

41. The method of claim 40 further comprising the step of resetting the charge in the integrator capacitor.

42. The method of claim 39 further comprising loading the integrator capacitor with first and second resistive loads and equalizing load current flowing through the first and second resistive loads.

43. The method of claim 42 further comprising the step of maintaining minimum, non-zero load currents through the first and second resistive loads.