Semiconductor memory device capable of realizing a chip with high operation reliability and high yield

  • US 6,424,588 B2
  • Filed: 12/28/2000
  • Issued: 07/23/2002
  • Est. Priority Date: 07/02/1998
  • Status: Expired due to Term
First Claim
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1. A semiconductor memory device comprising:

  • a memory cell array having memory cells or memory cell units formed by connecting at least one memory cell, said memory cells or memory cell units being arranged in an array form, wherein selection gate lines are formed by use of a mask having a data pattern in which the width of at least one of a word line and a selection gate line arranged on the end portion of said memory cell array is set larger than that of at least one of a word line and selection gate line arranged on the other portion of said memory cell array.

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