Method to form bump in bumping technology

• US 6,426,281 B1
• Filed: 01/16/2001
• Issued: 07/30/2002
• Est. Priority Date: 01/16/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Yen-Ming, Fan, Fu-Jier, Lin, Kuo-Wei, Fan, Yang-Tung, Peng, Chiou-Shian, Chu, Cheng-Yu, Lin, Shih-Jang
• Primary Examiner(s): Niebling, John F.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US09/759,911
• Time in Patent Office: 560 Days
• Field of Search: 438/612, 438/613, 438/614
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05022 the internal layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05027 the internal layer extending out of an opening
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/11902 Multiple masking steps
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 Argon [Ar]
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01022 Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A new method and processing sequence is provided for the creation of interconnect bumps. A layer of passivation is deposited over a contact pad and patterned, creating an opening in the layer of passivation that aligns with the contact pad. A layer of UBM metal is deposited over the layer of passivation, the layer of UBM is overlying the contact pad and limited to the immediate surroundings of the contact pad. The central surface of the layer of UBM is selectively electroplated after which a layer of solder or solder alloy is solder printed over the electroplated surface of the layer of UBM. A solder flux or paste is applied over the surface of the solder printed solder compound or solder alloy. Flowing of the solder or solder alloy creates the solder bump of the invention.

Claims

1. A method for forming a bump on a semiconductor surface, a contact pad having been provided on said semiconductor surface, comprising:

depositing a layer of passivation over said semiconductor surface including the surface of said contact pad;

patterning and etching said layer of passivation, creating an opening in said layer of passivation having a first diameter, partially exposing the surface of said contact pad over a surface area of said first diameter;

performing an in-situ sputter clean of the exposed surface of the contact pad;

plating a layer of Under Bump Metallurgy (UBM) over the surface of said layer of passivation, including said partially exposed surface of said contact pad, said layer of UBM comprising a barrier layer of titanium over which a seed layer of copper is deposited;

depositing a first layer of photoresist over the semiconductor surface of the layer of UBM;

patterning and etching said first layer of photoresist, leaving in place a layer of first photoresist that is aligned with said contact pad, partially exposing the surface of said layer of UBM;

etching said layer of UBM and said layer of passivation, removing said layer of UBM and said layer of passivation over said semiconductor surface where no layer of first photoresist is present, leaving a layer of remaining UBM and a layer of remaining passivation in place in an area overlying said contact pad;

removing said patterned and etched first layer of photoresist from above the surface of said semiconductor surface;

depositing a second layer of photoresist over the surface of said semiconductor surface, including the surface of said layer of remaining UBM;

patterning and etching said second layer of photoresist, creating an opening in said second layer of photoresist that is aligned with said contact pad, partially exposing the surface of said layer of remaining UBM;

electroplating the partially exposed surface of said layer of remaining UBM with a layer of copper over which a layer of nickel is electroplate, partially filling said opening created in said second layer of photoresist;

filling said opening created in said second layer of photoresist with a solder compound using methods of solder print;

applying a solder flux or paste to the surface of said solder compound;

removing said patterned and etched second layer of photoresist from above said semiconductor surface; and

reflowing the surface of said layer of solder or its alloys, forming the solder bump.

2. The method of claim 1 wherein said layer of passivation comprises PE Si₃N₄ deposited to a thickness between about 200 and 800 Angstrom.

3. The method of claim 1 wherein said layer of passivation is selected from the group consisting of SiO₂, a photosensitive polyimide, phosphorous doped silicon dioxide and titanium nitride, said layer of passivation is deposited to a thickness between about 200 and 800 Angstrom.

4. The method of claim 1 wherein said layer of Under Bump Metallurgy comprises a layer of chromium followed by a layer of copper followed by a layer of gold.

5. The method of claim 1 with an additional step of curing said second layer of photoresist, said additional step to be performed after said second layer of photoresist has been deposited and before said second layer of photoresist is patterned and etched.

6. The method of claim 5 wherein said curing said second layer of photoresist is performed in a N₂ gas ambient, at a temperature of between about 300 and 400 degrees C., for a time period between about 1.5 and 2.5 hours, and a pressure of 760 Torr.

7. The method of claim 1 wherein said passivation layer deposited over the surface of said semiconductor surface comprises a plurality of passivation layers.

8. The method of claim 7 wherein at least one of said plurality of passivation layers is selected from the group consisting of PE Si₃N₄ and SiO₂ and a photosensitive polyimide and phosphorous doped silicon dioxide and titanium nitride.

9. The method of claim 1 wherein said layer of Under Bump Metallurgy comprises a plurality of sub-layers of different metallic composition.

10. The method of claim 1 wherein said contact pad on said semiconductor surface is electrically connected with a semiconductor device with at least one conductive line of interconnect or with at least one conductive contact point.

11. The method of claim 1 wherein said etching said layer of UBM comprises sputter etching or wet etching.

12. The method of claim 1 wherein said semiconductor surface is selected from a group of surfaces comprising semiconductor substrates, printed circuit boards, flex circuits or a metallized or glass substrate or semiconductor device mounting support.

13. A method for forming a bump on a semiconductor surface, a contact pad having been provided on said semiconductor surface, comprising:

depositing one or more layers of passivation over said semiconductor surface including the surface of said contact pad, said one or more layers of passivation comprising PE Si₃N₄ deposited to a thickness between about 200 and 2000 Angstrom;

patterning and etching said one or more layers of passivation, creating an opening in said one or more layers of passivation having a first diameter, partially exposing the surface of said contact pad over a surface area of said first diameter;

performing an in-situ sputter clean of the exposed surface of the contact pad;

blanket plating a layer of Under Bump Metallurgy (UBM) over the surface of said layer of passivation, including said partially exposed surface of said contact pad, said layer of UBM comprising one or more layers of different metallic composition, said one or more layers of different metallic composition comprising at least one barrier layer of titanium and at least one seed layer of copper;

depositing a first layer of photoresist over the semiconductor surface of the layer of UBM;

patterning and etching said first layer of photoresist, creating a first layer of photoresist that is aligned with said contact pad, partially overlying and covering the surface of said layer of UBM, said covered surface of said layer of UBM being a surface area of said layer of UBM said needs to be retained in order to form said bump overlying said contact pad;

etching said layer of UBM and said layer of passivation, removing said layer of UBM and said layer of passivation that is not covered by said patterned and etched first layer of photoresist from above the surface of said semiconductor surface, creating a retained layer of UBM overlaying said contact pad;

removing said patterned and etched first layer of photoresist from the surface of said retained layer of UBM;

depositing a second layer of photoresist over the surface of said semiconductor surface, including the surface of said retained layer of UBM;

patterning and etching said second layer of photoresist, creating an opening having a bottom in said second layer of photoresist that aligns with said contact pad, partially exposing the surface of said retained layer of UBM;

electroplating a layer of copper over the bottom of said opening created in said second layer of photoresist followed by plating a layer of nickel over the surface of said plated layer of copper;

solder printing a layer of solder material or its alloy over the electroplated surface of nickel, filling said opening created in said second layer of photoresist;

baking said layer of solder material or its alloy, solidifying said layer of solder material or its alloy;

applying a flux to the surface of the layer of solder or its alloy;

removing said patterned second layer of photoresist from above the surface of said semiconductor surface; and

reflowing said layer of solder or its alloys, forming the solder bump.

14. The method of claim 13 with an additional step of curing said second layer of photoresist, said additional step to be performed after said second layer of photoresist has been deposited and before said layer of photoresist is patterned and etched, said curing of said second layer of photoresist being performed in a N₂ gas ambient, at a temperature of between about 300 and 400 degrees C., for a time period between about 1.5 and 2.5 hours, and a pressure of 760 Torr.

15. The method of claim 13 wherein at least one of said one or more passivation layers is selected from the group consisting of PE Si₃N₄, SiO₂, a photosensitive polyimide, phosphorous doped silicon dioxide and titanium nitride.

16. The method of claim 13 wherein said contact pad on said semiconductor surface is electrically connected with a semiconductor device with at least one conductive line of interconnect or with at least one conductive contact point.

17. The method of claim 13 wherein said semiconductor surface is selected from a group of surfaces comprising semiconductor substrates, printed circuit boards, flex circuits or a metallized or glass substrate or semiconductor device mounting support.