Flash memory cell with contactless bit line, and process of fabrication
First Claim
Patent Images
1. In a memory cell array:
- a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, source regions formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.
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Abstract
Memory cell array and process of fabrication in which a floating gate is formed on a substrate for each of a plurality of memory cells, a control gate is formed above and in vertical alignment with each of the floating gates, source regions are formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines are formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate is formed across the control gates, the floating gates, the bit lines and the source regions.
88 Citations
14 Claims
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1. In a memory cell array:
- a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, source regions formed in the substrate between and partially overlapped by first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.
- View Dependent Claims (5, 6, 7, 8)
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2. In a memory cell array:
- a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, the floating gates being wider than the control gates and having first and second edge portions which project laterally beyond the edges of the control gates, source regions formed in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between the second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.
- View Dependent Claims (3, 4)
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9. In a memory cell array:
- a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, the floating gates being wider and substantially thinner than the control gates and having first and second sharply rounded edge portions which project laterally beyond the edges of the control gates, source regions formed in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate between the second edge portions of the floating gates in adjacent ones of the cells, and a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions.
- View Dependent Claims (10, 11)
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12. In a memory cell array:
- a substrate, a plurality of memory cells positioned side-by-side on the substrate, each of the memory cells having a floating gate and a control gate which overlies the floating gate, source regions formed in the substrate between and partially overlapped by the first edge portions of the floating gates in adjacent ones of the cells, bit lines formed in the substrate midway between the second edge portions of the floating gates in adjacent ones of the cells, a select gate which crosses over the control gates, the floating gates, the bit lines and the source regions, and dielectric material between the floating gate and the control gate and between the control gate and the select gate, the dielectric material between the floating gate and the control gate being substantially thinner than the dielectric material between the control gate and the select gate.
- View Dependent Claims (13, 14)
Specification