Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals

• US 6,429,120 B1
• Filed: 01/18/2000
• Issued: 08/06/2002
• Est. Priority Date: 01/18/2000
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): LEBENTRITT, MICHAEL
• Application Number:
  US09/488,098
• Time in Patent Office: 931 Days
• Field of Search: 438/653, 438/654, 438/655, 438/635, 438/637, 438/688, 438/660, 257/754, 257/758, 257/767, 257/768
• US Class Current: 438/635
• CPC Class Codes: C23C 14/3471 Introduction of auxiliary energy into the plasma
• CPC Class Codes: C23C 16/517 using a combination of discharges covered by two or more of groups C23C16/503 - C23C16/515
• CPC Class Codes: G02F 1/13454 Drivers integrated on the active matrix substrate G02F1/136277 takes precedence
• CPC Class Codes: H01J 37/3408 Planar magnetron sputtering
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76856 by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

Integrated circuits, the key components in thousands of electronic and computer products, include interconnected networks of electrical components. The components are typically wired, or interconnected, together with aluminum wires. In recent years, researchers have begun using copper instead of aluminum to form integrated-circuit wiring, because copper offers lower electrical resistance and better reliability at smaller dimensions. However, use of copper typically requires forming a diffusion barrier to prevent contamination of other parts of an integrated circuit and forming a seed layer to facilitate copper plating steps. Unfortunately, typical diffusion barrier materials add appreciable resistance to the copper wiring, and thus negate some of the advantages of using copper. Moreover, conventional methods of forming the diffusion barriers and seed layers require use of separate wafer-processing chambers, giving rise to transport delays and the introduction of defect-causing particles. Accordingly, the inventors devised unique wafer-processing chambers and methods of forming barrier and seed layers. One embodiment of the wafer-processing chamber includes equipment for physical vapor deposition and equipment for chemical vapor deposition to facilitate formation of diffusion barriers and seed layers within one chamber. One of the unique methods entails forming a composition of tungsten, silicon, and nitrogen (WSi_xN_y) and then depositing a copper-, silver-, or gold-based seed layer on the composition, all within a single wafer-processing chamber to promote fabrication efficiency and reduce defects.

Claims

1. A method of making a diffusion barrier and a seed layer in an integrated-circuit assembly, comprising:

forming a diffusion barrier on a surface of an integrated-circuit assembly in a first wafer-processing chamber using chemical-vapor deposition; and

forming a seed layer on at least a portion of the diffusion barrier in the first wafer-processing chamber using physical-vapor deposition.

2. A method of making copper, silver, or gold interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber using chemical-vapor deposition; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber using physical-vapor deposition.

3. The method of claim 2 wherein forming the insulative layer including one or more holes or trenches, comprises:

depositing or growing a silicon oxide layer; and

forming one or more holes or trenches in the silicon oxide layer.

4. A method of making copper, silver, or gold interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber,

wherein forming the diffusion barrier in the wafer-processing chamber comprises forming a graded composition of WSi_x, where x varies from 2.0 to 2.5.

5. A method of making copper, silver, or gold interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber,

wherein forming the diffusion barrier in the wafer-processing chamber comprises;

forming a graded composition of WSi_x, where x varies from 2.0 to 2.5; and

nitriding the graded composition of WSi_x.

6. The method of claim 5 wherein nitriding the graded composition of WSi_x comprises introducing ECR plasma in the first processing chamber and exciting the introduced plasma with argon gas.

7. A method of making copper, silver, or gold interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber,

wherein forming the diffusion barrier in the first wafer-processing chamber comprises;

introducing tungsten hexaflouride and hydrogen gases into the wafer processing chamber for a predetermined amount of time;

introducing silane gas into the chamber a first predetermined time after introducing the tungsten hexaflouride gas; and

terminating introduction of the silane gas a second predetermined time before terminating introduction of the tungsten hexaflouride and hydrogen gases into the first wafer-processing chamber.

8. The method of claim 7, wherein the first and second times are in the range of about one to about three seconds.

9. A method of making copper, silver, or gold interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber; and

forming a copper-based, silver-based, or gold-based conductive structure on at least a portion of the diffusion barrier in the first wafer-processing chamber,

wherein forming the conductive structure comprises;

ionized sputtering or DC magnetron sputtering of a copper-based material onto at least a portion of the diffusion barrier; and

electroplating copper-based material onto the sputtered copper-based material.

10. A method of making copper, silver, or gold interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, with the diffusion barrier comprising a graded composition of WSi_x, where x varies from 2.0 to 2.5; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber.

11. The method of claim 10 wherein forming the insulative layer including one or more holes or trenches, comprises:

depositing or growing a silicon oxide layer; and

forming one or more holes or trenches in the silicon oxide layer.

12. The method of claim 10, wherein forming the conductive structure comprises sputtering or electroplating a copper-, silver-, or gold-based material onto at least a portion of the diffusion barrier.

13. A method of making copper-, silver-, or gold-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, wherein forming the diffusion barrier includes;

forming a graded composition of WSi_x, where x varies from 2.0 to 2.5; and

nitriding the graded composition of WSi_x; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber.

14. The method of claim 13 wherein nitriding the graded composition of WSi_x comprises introducing ECR plasma in the first processing chamber and exciting the introduced plasma with argon gas.

15. A method of making copper-, silver-, or gold-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, wherein forming the diffusion barrier includes;

introducing tungsten hexaflouride and hydrogen gases into the wafer processing chamber for a predetermined amount of time;

introducing silane gas into the chamber a first predetermined time after introducing the tungsten hexaflouride gas;

terminating introduction of the silane gas a second predetermined time before terminating introduction of the tungsten hexaflouride and hydrogen gases into the chamber; and

introducing nitrogen and argon gases and an ECR plasma in the first processing chamber; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber.

16. The method of claim 15, wherein the first and second times are in the range of about one to about three seconds.

17. The method of claim 15, wherein forming the copper-based, silver-based, or gold-based structure comprises sputtering or electroplating a copper-, silver-, or gold-based material onto at least a portion of the diffusion barrier.

18. A method of making copper-, silver-, or gold-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, wherein forming the diffusion barrier includes;

introducing tungsten hexaflouride and hydrogen gases into the wafer processing chamber for a predetermined amount of time;

introducing silane gas into the chamber a first predetermined time after introducing the tungsten hexaflouride gas;

terminating introduction of the silane gas a second predetermined time before terminating introduction of the tungsten hexaflouride and hydrogen gases into the chamber; and

introducing nitrogen and argon gases and an ECR plasma in the first processing chamber; and

forming a copper-based, silver-based, or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber, wherein forming the conductive structure comprises;

ionized sputtering or DC magnetron sputtering of a copper-based, silver-based, or gold-based material onto at least a portion of the diffusion barrier; and

electroplating copper-based material onto the sputtered copper-based material.

19. A method of making copper-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, wherein forming the diffusion barrier includes;

introducing tungsten hexaflouride and hydrogen gases into the wafer processing chamber for a predetermined amount of time;

introducing silane gas into the chamber a first predetermined time after introducing the tungsten hexaflouride gas;

terminating introduction of the silane gas a second predetermined time before terminating introduction of the tungsten hexaflouride and hydrogen gases into the chamber; and

introducing nitrogen and argon gases and an ECR plasma in the first processing chamber; and

forming a copper-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber, wherein forming the conductive structure comprises;

ionized sputtering or DC magnetron sputtering of a copper-based, silver-based, or gold-based material onto at least a portion of the diffusion barrier; and

electroplating copper-based material onto the sputtered copper-based material.

20. A method of making silver- or gold-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, wherein forming the diffusion barrier includes;

introducing tungsten hexaflouride and hydrogen gases into the wafer processing chamber for a predetermined amount of time;

introducing silane gas into the chamber a first predetermined time after introducing the tungsten hexaflouride gas;

terminating introduction of the silane gas a second predetermined time before terminating introduction of the tungsten hexaflouride and hydrogen gases into the chamber; and

introducing nitrogen and argon gases and an ECR plasma in the first processing chamber; and

forming a silver-based or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber, wherein forming the silver-based or gold-based structure comprises;

ionized sputtering or DC magnetron sputtering of a silver-based or a gold-based material onto at least a portion of the diffusion barrier; and

electroplating a silver-based or a gold-based material onto the sputtered copper-based material.

21. A method of making copper-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, with the diffusion barrier comprising a graded composition of WSi_x, where x varies from 2.0 to 2.5; and

forming a copper-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber.

22. A method of making silver-based or gold-based interconnects for an integrated circuit, comprising:

forming an insulative layer including one or more holes or trenches;

forming a diffusion barrier in one or more of the holes or trenches in a first wafer-processing chamber, with the diffusion barrier comprising a graded composition of WSi_x, where x varies from 2.0 to 2.5; and

forming a silver-based or gold-based structure on at least a portion of the diffusion barrier in the first wafer-processing chamber.

23. A method of making an integrated circuit, comprising:

chemical-vapor depositing a first material on a first surface within a first processing chamber; and

physical-vapor depositing a second material on a second surface within the first processing chamber.

24. The method of claim 23 wherein the first and second materials have different chemical compositions.

25. The method of claim 23 wherein physical-vapor depositing occurs before or after chemical-vapor depositing.