System and method for high-level test planning for layout

  • US 6,434,733 B1
  • Filed: 03/24/1999
  • Issued: 08/13/2002
  • Est. Priority Date: 03/24/1999
  • Status: Expired due to Term
First Claim
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1. A computer implemented process for electronic design automation, said process comprising the steps of:

  • receiving an HDL description of an integrated circuit design;

    generating a scannable netlist based on said HDL description, said scannable netlist comprising a scan chain;

    partitioning said scan chain into a plurality of sets of re-orderable scan cells, wherein partitioning information which describes the scan cells of each set is generated; and

    based on said partitioning information, re-ordering scan cells of said scan chain during layout processes of said integrated circuit design, said step of re-ordering only re-ordering scan cells of a same set and not re-ordering scan cells of different sets.

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