DRAM refresh timing adjustment device, system and method

  • US 6,438,057 B1
  • Filed: 07/06/2001
  • Issued: 08/20/2002
  • Est. Priority Date: 07/06/2001
  • Status: Expired due to Term
First Claim
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1. An apparatus, comprising:

  • a semiconductor package including at least one connection pin;

    at least one dynamic random access memory (DRAM) array disposed within the package; and

    at least one temperature sensor in thermal communication with the DRAM array, operable to produce a signal indicative of a temperature of the DRAM array, and coupled to the at least one connection pin such that the signal may be provided to external circuitry, wherein the DRAM array is refreshed at a rate that decreases as the temperature of the DRAM array decreases and that increases as the temperature of the DRAM array increases.

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