Reconfigurable logic for a computer

• US 6,438,737 B1
• Filed: 02/15/2000
• Issued: 08/20/2002
• Est. Priority Date: 02/15/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Morelli, John, Kendall, H. Richard
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/505,059
• Time in Patent Office: 917 Days
• Field of Search: 716/16, 326/38-40
• US Class Current: 326/38
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A system is disclosed including a reconfigurable logic circuit having programmable logic, a first memory, and a second memory. The first memory stores a number of logic designs each operable to configure the programmable logic. Also included is a computer coupled to the reconfigurable logic circuit that concurrently executes one or more application programs and an interface program. The application programs generate a number of requests to utilize the reconfigurable logic circuit and the interface program responds to the requests by opening a number of coexisting program interfaces. These interfaces each correspond to an instance of one of the logic designs stored in the first memory. The reconfigurable logic circuit is responsive to the interface program to provide a number of interface buffers in the second memory that each belong to a corresponding one of the interfaces and are each operable to store data passing between the computer and the reconfigurable logic circuit.

Claims

1. A system comprising:

a reconfigurable logic circuit including programmable logic, a first memory and a second memory, said first memory being arranged to store a number of logic designs each operable to configure said programmable logic;

a computer coupled to said reconfigurable logic circuit, said computer being operable to concurrently execute one or more application programs and an interface program, the one or more application programs generating a number of requests to utilize said reconfigurable logic circuit, the interface program being responsive to the requests to open a number of coexisting program interfaces between the one or more application programs and said reconfigurable logic circuit, the program interfaces each corresponding to one of the logic designs stored in said first memory;

wherein the reconfigurable logic circuit, in response to the interface program, provides a number of interface buffers in the second memory, each interface buffer corresponding to one of the program interfaces; and

wherein each provided interface buffer is operable to store data passing between the computer and the reconfigurable logic circuit.

2. The system of claim 1, wherein said reconfigurable logic circuit includes design loading logic coupled between said programmable logic and said first memory to control loading of said programmable logic with any of the logic designs in accordance with the interface program.

3. The system of claim 1, wherein said reconfigurable logic circuit is a field programmable gate array configured to include a first portion with logic to interface with said computer, a second portion with logic to interface with said second memory, and a third portion to be variably configured in accordance with one of the logic designs.

4. The system of claim 1, wherein the second memory includes a first memory device with a first one of the interface buffers for a first one of the logic designs and a second memory device with a second one of the interface buffers for a second one of the logic designs, and said reconfigurable logic circuit provides for simultaneous access to said first memory device by said programmable logic and said second memory device by said computer during operation of said programmable logic in accordance with the first one of the logic designs.

5. The system of claim 1, wherein the interface buffers include an input buffer, an output buffer, and a state buffer for each of the interfaces.

6. The system of claim 1, wherein said computer includes one or more processors, a main memory, and an input/output bridge coupled together by a processor bus, said input/output bridge is coupled to an input/output bus having a bandwidth that is less than a bandwidth of said processor bus, and said programmable logic is connected to said processor bus and mapped to one or more memory locations accessible by the one or more processors.

7. The system of claim 6, wherein said interface program is operable to allocate an overflow memory space in said main memory to store interface information when said second memory is full.

8. A system, comprising:

a digital processor bus operable to interconnect a processor cluster;

a reconfigurable logic device;

a main memory;

one or more processors coupled to said reconfigurable logic device and said main memory by said processor bus, at least one of said one or more processors being operable to access said reconfigurable logic device;

an input/output bridge coupled to said processor bus;

an input/output bus coupled to said input/output bridge to isolate said input/output bus from said processor bus;

an input/output module coupled to said input/output bus; and

wherein at least one of said one or more processors transfers data to said reconfigurable logic device with a first latency time and to said input/output module with a second latency time, said second latency time being greater than said first latency time.

9. The system of claim 8, wherein said reconfigurable logic device includes programmable logic, a first memory to store a plurality of logic designs operable to configure said programmable logic, and a second memory operable to provide at least one interface buffer for each of the logic designs.

10. The system of claim 9, wherein:

said programmable logic includes a volatile field programmable gate array;

said reconfigurable logic device includes nonvolatile loading logic coupled between said programmable logic and said first memory to load said programmable logic with a selected one the logic designs; and

said programmable logic is programmed to include a first portion with logic to interface with said computer, a second portion with logic to interface with said second memory, and a third portion to be variably configured in accordance with the selected one of the logic designs.

11. The system of claim 8, wherein said at least one of the one or more processors is operable to access said reconfigurable logic device by mapping said reconfigurable logic device to one or more memory locations.

12. The system of claim 8, wherein said input/output bus is of a PCI type and said processor bus operates with a first bandwidth and said input/output bus operates with a second bandwidth less than said first bandwidth.

13. An apparatus, comprising:

a reconfigurable logic circuit configured to communicate through a computer interface, said reconfigurable logic circuit including

programmable logic;

a first memory device operatively coupled to said programmable logic to store first interface information for a first logic design;

a second memory device operatively coupled to said programmable logic to store second interface information for a second logic design; and

memory interface logic operable to simultaneously provide local access to said first interface information in said first memory by said programmable logic and remote access to said second interface information in said second memory through said memory interface logic during configuration of said programmable logic with the first logic design, and change access modes to simultaneously provide local access to said second interface information in said second memory with said programmable logic and remote access to said first interface information in said first memory through said memory interface logic in response to configuring said programmable logic with said second logic design.

14. The apparatus of claim 13, wherein said memory interface logic is operable to provide priority to a remote access when in conflict with a local access by said programmable logic.

15. The apparatus of claim 13, wherein said memory interface logic is at least partially defined by said programmable logic and said first memory device is coupled to said memory interface logic by a first memory bus and said second memory device is coupled to said memory interface logic by a second memory bus.

16. The apparatus of claim 13, wherein said first memory device is arranged with a scratch space for selective access by said programmable logic and said first interface information includes a number of interface control structures, said interface control structures each including a pointer to an input buffer and an output buffer.

17. The apparatus of claim 13, further comprising a computer with one or more processors and a main memory coupled together by a processor cluster bus, said processor cluster bus being coupled to said reconfigurable logic circuit to provide the computer interface.

18. The apparatus of claim 13, wherein said reconfigurable logic circuit includes a nonvolatile memory to store a plurality of different logic designs and nonvolatile design loading logic, said loading logic being connected between said programmable logic and said nonvolatile memory to control loading of a designated one of the different logic designs.

19. An apparatus, comprising:

a reconfigurable logic circuit configured with a computer interface, said reconfigurable logic circuit including

programmable logic;

a first memory to dynamically store a number of logic designs each selected to configure said programmable logic;

a second memory to dynamically store interface control information for each of the logic designs, the interface control information relating to one or more buffers allocated in said second memory for each of the logic designs to transmit data through said computer interface.

20. The apparatus of claim 19, wherein said second memory is further operable to store a scratch space accessible by said programmable logic.

21. The apparatus of claim 20, wherein the scratch space is dynamically allocated in said second memory in an address space between the interface control information for each of the logic designs and the one or more buffers for each of the logic designs.

22. The apparatus of claim 19, wherein the one or more buffers include an input buffer and an output buffer for each of the logic designs.

23. The apparatus of claim 22, wherein the interface control information for each of the logic designs includes a first pointer to the input buffer and second pointer to the output buffer, and data relating to size of each of the input buffer and the output buffer.

24. The apparatus of claim 19, wherein the interface control information includes data relating to time of last use of a respective one of the logic designs.

25. The apparatus of claim 24, wherein the interface control information includes a logic design identifier for the respective one of the logic designs.

26. The apparatus of claim 19, further comprising a computer with one or more processors and a main memory coupled together by a processor cluster bus, said processor cluster bus being coupled to said computer interface of said reconfigurable logic circuit.

27. The apparatus of claim 19, wherein said first memory is nonvolatile and said programmable logic includes a volatile field programmable gate array, and said reconfigurable logic circuit includes nonvolatile loading logic coupled between said programmable logic and said nonvolatile memory to control loading of a designated one of the logic designs.

28. An apparatus, comprising:

a reconfigurable logic circuit including programmable logic, design loading logic connected to said programmable logic, and one or more memory devices including;

a first memory space operable to store a number of logic designs for said programmable logic, said first memory space being accessible by said loading logic to selectively load one or more of said logic designs into said programmable logic; and

a second memory space operable to store a number of interface control structures each corresponding to a different instance of one of the logic designs, said second memory space being accessible by said programmable logic.

29. The apparatus of claim 28, wherein said one or more memory devices includes at least one nonvolatile memory device defining said first memory space.

30. The apparatus of claim 28, wherein said loading logic is coupled to said programmable logic and operable to load one or more of said logic designs from said first memory space into said programmable logic to configure said programmable logic with first interface logic and second interface logic.

31. The apparatus of claim 30, further comprising a computer with a processor bus coupled to said first interface logic and wherein said first interface logic and said loading logic cooperate to store one or more of the logic designs in said first memory space, and said second interface logic is operable to access said second memory space.

32. The apparatus of claim 28, wherein the interface control structures each include a data buffer.

33. The apparatus of claim 28, wherein the interface control structures each include an identifier for the one of the logic designs, a pointer to a buffer space, and data representative of time of last use of the one of the logic designs.

34. A method, comprising:

operating a computer coupled to a reconfigurable logic circuit, the reconfigurable logic circuit including programmable logic, a first memory device, and a second memory device;

storing first interface information in the first memory device for a first logic design and second interface information in the second memory for a second logic design;

providing simultaneous access to the first interface information by the programmable logic and the second interface information by the computer during operation of the programmable logic in accordance with the first logic design; and

providing simultaneous access to the second interface information by the programmable logic and the first interface information by the computer during operation of the programmable logic in accordance with the second logic design.

35. The method of claim 34, further comprising accessing the first memory device with the computer while the programmable logic is configured with the first logic design.

36. The method of claim 34, further comprising changing a mode of access to the first memory device and the second memory device in response to reconfiguration of the programmable logic.

37. The method of claim 34, wherein the first interface information includes a first input buffer and a first output buffer and the second interface information includes a second input buffer and a second output buffer.

38. The method of claim 34, further comprising:

executing one or more application programs and an interface program on the computer; and

establishing two coexisting program interfaces between the computer and the reconfigurable logic circuit with the interface program, a first one of the program interfaces being for the first logic design and a second one of the program interfaces being for the second logic design.

39. The method of claim 34, wherein the first interface information includes a control structure, a scratch space, a first interface buffer, and a second interface buffer and further comprising:

storing an identifier for the first logic design, a first pointer to the first interface buffer, a second pointer to the second interface buffer, data representing time of last use for the first logic design, and data relating to size of the first interface buffer and the second interface buffer in the control structure.

40. A system, comprising:

a reconfigurable logic circuit including programmable logic and a local memory, said local memory being operable to store interface information relating to a number of logic designs for said programmable logic;

a computer coupled to said reconfigurable logic circuit, said computer including one or more processors and a main memory coupled to said one or more processors, said computer being operable to execute one or more application programs and a interface program, the one or more application programs being operable to generate a number of requests to utilize said reconfigurable logic circuit, the interface program being responsive to the requests to control application of the logic designs to said programmable logic, the interface program being operable to selectively allocate a memory space in said main memory for overflow of said local memory.

41. The system of claim 40, wherein said local memory includes one or more memory devices operable to store the interface information and one or more other memory devices operable to store the logic designs, the one or more other memory devices being nonvolatile.

42. The system of claim 41, wherein the interface program is operable to determine a least recently used one of the logic designs stored in said one or more other memory devices based on the interface information and selectively store said least recently used one of the logic designs in said memory space of said main memory to load a different logic design in said one or more other memory devices of said local memory.

43. The system of claim 41, wherein the reconfigurable logic circuit includes loading logic coupled between said one or more other memory devices and said programmable logic.

44. The system of claim 40, wherein the interface program is operable to establish a number of coexisting program interfaces in response to the requests, the program interfaces each corresponding to a different one of the logic designs.

45. The system of claim 40, wherein said computer includes a processor bus to couple said main memory and said one or more processors together, an input/output bridge coupled to said processor bus, and an input/output bus coupled to said input/output bridge.

46. The system of claim 40, wherein the interface information includes a number of interface buffers allocated in said local memory, and said interface program is operable to store data intended for one of said buffers in said memory space when the size of the one of the buffers is insufficient to receive the data.

47. A method, comprising:

executing at least one application program and an interface program on a computer coupled to a reconfigurable logic circuit including programmable logic and a local memory;

storing several logic designs in the local memory with the interface program, the logic designs each being operable to configure the programmable logic;

opening two or more coexisting program interfaces between the at least one application program and the reconfigurable logic circuit with the interface program after said storing, the program interfaces each corresponding to a selected one of the logic designs;

writing input data to the reconfigurable logic circuit for a selected one of the program interfaces;

configuring the programmable logic with the selected one of the logic designs;

processing the input data with the programmable logic after said configuring;

reading output data from the reconfigurable logic circuit for the selected one of the program interfaces after said processing;

closing the selected one of the program interfaces after said reading with the interface program, other of the program interfaces remaining open; and

replacing a first one of the logic designs with a different logic design.

48. The method of claim 47, wherein the computer includes a main memory and further comprising:

allocating a memory space in the main memory with the interface program;

determining a least recently used one of the logic designs stored in the local memory with the interface program; and

storing the least recently used one of the logic designs in the memory space to provide space in the local memory to load another logic design.

49. The method of claim 47, further comprising:

providing a request to the interface program to process data with a designated one of the logic designs; and

determining status of the request with the interface program; and

performing a software routine to emulate the designated one of the logic designs in response to a first status of the request; and

configuring the programmable logic with the designated one of the logic designs in response to a second status of the request.

50. The method of claim 47, wherein the selected one of the logic designs is the same for each of the program interfaces.

51. The method of claim 47, wherein the selected one of the logic designs is different for each of the program interfaces.

52. The method of claim 47, wherein the interface program includes a first routine to open a specified program interface, a second routine to write data to the reconfigurable logic circuit for the specified program interface, a third routine to read information from the reconfigurable logic circuit for the specified program interface, and a fourth routine to close the specified program interface.

53. The method of claim 52, wherein the interface program includes a fifth routine to provide a designated logic design to the reconfigurable logic circuit and a sixth routine to remove the designated logic design.

54. A method, comprising:

operating a computer coupled to programmable logic;

concurrently executing two or more application programs with the computer, the application programs each generating at least one of a plurality of requests to utilize the programmable logic device during said executing;

processing the requests of each of the application programs with an interface program executed by the computer; and

controlling the programmable logic with the interface program to reconfigure the programmable logic device a number of times during said executing in accordance with the requests.

55. The method of claim 54, establishing a number of coexisting program interfaces with the interface program in response to the requests, the program interfaces each corresponding to a designated one of a number of logic designs for the programmable logic.

56. The method of claim 55, wherein the computer is coupled to a reconfigurable logic circuit including the programmable logic and a local memory, and further comprising storing the logic designs in the local memory with the interface program.

57. The method of claim 54, wherein the interface program includes a first routine to open a specified program interface, a second routine to write data for the specified program interface, a third routine to read data for the specified program interface, and a fourth routine to close the specified program interface.

58. The method of claim 54, wherein the computer includes a main memory and the programmable logic is coupled to a local memory, and further comprising:

storing a number of logic designs in the local memory;

allocating a memory space in the main memory with the interface program;

determining a least recently used one of the logic designs stored in the local memory with the interface program; and

storing the least recently used one of the logic designs in the memory space to provide space in the local memory to load another logic design.

59. The method of claim 54, further comprising:

determining status of one of the requests associated with a designated logic design; and

performing a software routine to emulate the designated logic design in response to a first status of the one of the requests; and

configuring the programmable logic with the designated logic design in response to a second status of the one of the requests.

60. The method of claim 54, wherein the programmable logic includes a field programmable gate array, the programmable logic is included in a reconfigurable logic circuit, and the reconfigurable logic circuit further includes a first memory operable to store interface information and a second memory operable to store a number of logic designs for the programmable logic.

61. A computer-readable device storing a number of instructions for execution by a computer coup led to a reconfigurable logic circuit, the reconfigurable logic circuit including programmable logic and a local memory to store a number of logic designs each operable to configure the programmable logic, the instructions being arranged to provide a interface program responsive to requests to utilize the reconfigurable logic circuit from a number of application programs executed by the computer, the interface program comprising:

a first routine executable a number of times to open a corresponding number of coexisting program interfaces between the application programs and the reconfigurable logic circuit, said program interfaces each providing for configuration of the programmable logic with a corresponding one of a number of instances of one or more of several logic designs;

a second routine to provide input data to the reconfigurable logic circuit for a selected one of said program interfaces opened by said first routine for processing by the programmable logic when configured with said corresponding one of said instances;

a third routine to request output data from the reconfigurable logic circuit for said selected one of said program interfaces, said output data being generated by the programmable logic when configured by said corresponding one of said instances; and

a fourth routine to selectively close a specified one of said program interfaces established with said first routine, said fourth routine leaving other of said program interfaces open.

62. The device of claim 61, wherein the interface program further comprises a fifth routine to remove a designated one of said program interfaces established with said first routine.

63. The device of claim 62, wherein the interface program includes a sixth routine executed one or more times to store the logic designs.

64. The device of claim 61, wherein the interface program is operable to determine status of a request from one of the application programs to implement a designated one of the logic designs, to initiate execution of a software routine to emulate the designated one of the logic designs in response to a first status indication, and to initiate configuration of the programmable logic with the designated one of the logic designs in response to a second status indication.

65. The device of claim 61, wherein the computer includes a main memory and the interface program is operable to allocate and manage a memory space in the main memory for overflow from the local memory.