Method and apparatus for vertically locking input and output signals

• US 6,441,658 B1
• Filed: 08/14/2001
• Issued: 08/27/2002
• Est. Priority Date: 08/26/2000
• Status: Expired due to Term

• Current Assignee: RGB Systems Incorporated
• Original Assignee: RGB Systems Incorporated
• Inventors: Taraci, Brian Richard, Truong, Duy Duc
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): NGUYEN, LINH M
• Application Number:
  US09/930,749
• Publication Number:
  US 20020041335A1
• Time in Patent Office: 378 Days
• Field of Search: 327/146, 327/147, 327/149, 327/150, 327/151, 327/155, 327/156, 327/159, 327/160, 327/158, 327/166, 327/153, 386/17, 386/28, 386/41, 386/84, 348/194, 348/505, 348/540, 348/547
• US Class Current: 327/147
• CPC Class Codes: G09G 5/006 Details of the interface to the display terminal specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04
• CPC Class Codes: H03L 7/235 Nested phase locked loops
• CPC Class Codes: H04N 21/4113 PC
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/268 Signal distribution or switching
• CPC Class Codes: H04N 5/46 for receiving on more than one standard at will deflecting circuits of multi-standard receivers H04N3/27
• CPC Class Codes: H04N 5/74 Projection arrangements for image reproduction, e.g. using eidophor
• CPC Class Codes: H04N 7/012 Conversion between an interlaced and a progressive signal for graphics images G09G2310/0229
• CPC Class Codes: H04N 7/104 Switchers or splitters
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence
• CPC Class Codes: H04N 9/642 Multi-standard receivers

Abstract

This invention describes a method and apparatus for vertically locking input and output video frame rates. The output vertical sync pulse is locked in phase with the input vertical sync pulse, regardless of the input format and frequency. The output resolution, horizontal refresh rate, and delay are all user selectable. Two Phase Locked Loops are connected in series to achieve vertical lock between the input and output frames. Locking the vertical sync pulses between the input and output frames will eliminate mixing of pixels from different input frames in one output frame. The first Phase Locked Loop generates the output pixel clock required to satisfy the user'"'"'s display preferences but may not precisely represent the desired output pixel clock required for frame locking because current Phase Locked Loops use integer dividers. A second Phase Locked Loop adjusts its output, which is the reference frequency to the first Phase Locked Loop, until a lock is achieved. A free running oscillator measures the frequency of the incoming video and sends its output to a micro-controller that computes the divider required in the Phase Locked Loop based on user selected output resolution. The user may also adjust the delay between the vertical input and output video frames.

Claims

1. A method for vertically locking input and output signals comprising:

obtaining a continuous input video signal having an input vertical sync frequency;

generating a first divider value from said continuous input video signal, said first divider value being a positive integer number;

generating a reference frequency using a first frequency generator having a first adjustable output with a nominal frequency greater than zero, wherein said reference frequency is adjustable by adjusting said first adjustable output of said first frequency generator about said nominal frequency using an adjustment signal;

generating a pixel clock frequency from said reference frequency using said first divider value;

generating an output vertical sync frequency from said pixel clock frequency; and

adjusting said reference frequency to obtain a lock between said input vertical sync frequency and said output vertical sync frequency by generating said adjustment signal from an error between said input vertical sync frequency and said output vertical sync frequency.

2. The method of claim 1, wherein said input vertical sync frequency is indicated by a vertical sync pulse occurring at said input vertical sync frequency thus having a plurality of input vertical sync pulses in said continuous input video signal.

3. The method of claim 2, wherein said input vertical sync frequency is determined by counting a number of pulses of a free running oscillator occurring between two adjacent input vertical sync pulses of said plurality of input vertical sync pulses, wherein said free running oscillator has a frequency equal to said nominal frequency of said first frequency generator.

4. The method of claim 1, wherein said reference frequency is generated by dividing said first adjustable output of said first frequency generator by a second divider value, wherein said second divider value is a positive integer number.

5. The method of claim 4, wherein said generating said first divider value from said continuous input video signal comprises:

obtaining a desired video output vertical resolution;

obtaining a desired video output horizontal resolution; and

generating an intermediate value by dividing a product of said input vertical sync frequency, said desired video output horizontal resolution, said desired video output vertical resolution, and said second divider value, by said nominal frequency, said intermediate value having an integer portion and a fractional portion;

setting said first divider value to said integer portion of said intermediate value.

6. The method of claim 1, wherein said generating said pixel clock frequency comprises:

generating said pixel clock frequency using a second frequency generator having a second adjustable output with a nominal frequency equal to zero, said second frequency generator using an input error signal to generate said second adjustable output, wherein said second adjustable output is said pixel clock frequency; and

generating said error signal by comparing said reference frequency with an intermediate frequency generated by dividing said pixel clock frequency by said first divider value.

7. The method of claim 6, wherein said error signal is further filtered before being passed to said second frequency generator.

8. The method of claim 1, wherein said generating said output vertical sync frequency comprises:

obtaining a desired video output horizontal resolution and a desired video output vertical resolution;

generating a pixel counter by counting cycles of said pixel clock;

generating an output horizontal sync frequency from said pixel counter;

generating a line counter by counting cycles in said output horizontal sync frequency;

generating said output vertical sync frequency from said line counter;

restarting said pixel counter when said pixel counter reaches said desired video output horizontal resolution; and

restarting said line counter when said line counter reaches said desired video output vertical resolution.

9. The method of claim 8, wherein a user provides said desired video output horizontal resolution and said desired video output vertical resolution, and wherein said desired video output horizontal resolution and said desired video output vertical resolution have pixels required for blanking.

10. The method of claim 8, wherein said generating said output horizontal sync frequency comprises:

asserting a horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync start number; and

resetting said horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync end number.

11. The method of claim 8, wherein said generating said output vertical sync frequency comprises:

asserting a vertical sync pulse when said line counter is equivalent to a user programmable vertical sync start number; and

resetting said vertical sync pulse when said line counter is equivalent to a user programmable vertical sync end number, wherein said start number and said end number may be adjusted to cause phase shift between said input vertical sync pulse and said output vertical pulse.

12. An apparatus for vertically locking input and output signals comprising:

a continuous input video signal having an input vertical sync frequency;

means for generating a first divider value from said continuous input video signal, said first divider value being a positive integer number;

a first frequency generator for generating a reference frequency, said first frequency generator having a first adjustable output with a nominal frequency greater than zero, wherein said reference frequency is adjustable by adjusting said first adjustable output of said first frequency generator about said nominal frequency using an adjustment signal;

a second frequency generator for generating a pixel clock frequency from said reference frequency using said first divider value;

means for generating an output vertical sync frequency from said pixel clock frequency; and

means for generating said adjustment signal from an error between said input vertical sync frequency and said output vertical sync frequency, wherein said adjustment signal is used for adjusting said reference frequency until a lock is obtained between said input vertical sync frequency and said output vertical sync frequency.

13. The apparatus of claim 12, wherein said input vertical sync frequency is indicated by a vertical sync pulse occurring at said input vertical sync frequency thus having a plurality of input vertical sync pulses in said continuous input video signal.

14. The apparatus of claim 13, wherein said input vertical sync frequency is determined by counting a number of pulses of free running oscillator occurring between two adjacent input vertical sync pulses of said plurality of input vertical sync pulses, wherein said free running oscillator has a frequency equal to said nominal frequency of said first frequency generator.

15. The apparatus of claim 12, wherein said reference frequency is generated by dividing said first adjustable output of said first frequency generator by a second divider value, wherein said second divider value is a positive integer number.

16. The apparatus of claim 15, wherein said generating said first divider value from said continuous input video signal comprises:

obtaining a desired video output vertical resolution;

obtaining a desired video output horizontal resolution; and

generating an intermediate value by dividing a product of said input vertical sync frequency, and desired video output horizontal resolution, said desired video output vertical resolution, and said second divider value, by said nominal frequency, said intermediate value having an integer portion and a fractional portion;

setting said first divider value to said integer portion of said intermediate value.

17. The apparatus of claim 12, wherein said second frequency generator uses an error signal to generate a second adjustable output with a nominal frequency equal to zero, said second adjustable output being said pixel clock frequency, and said generating said pixel clock frequency comprising:

generating said error signal by comparing said reference frequency with an intermediate frequency generated by dividing said pixel clock frequency by said first divider value.

18. The apparatus of claim 17, wherein said error signal is further filtered before being passed to said second frequency generator.

19. The apparatus of claim 12, wherein said generating said output vertical sync frequency comprises:

obtaining a desired video output horizontal resolution and a desired video output vertical resolution;

generating a pixel counter by counting cycles of said pixel clock;

generating an output horizontal sync frequency from said pixel counter;

generating a line counter by counting cycles in said output horizontal sync frequency;

generating said output vertical sync frequency from said line counter;

restarting said pixel counter when said pixel counter reaches said desired video output horizontal resolution; and

restarting said line counter when said line counter reaches said desired video output vertical resolution.

20. The apparatus of claim 19, wherein a user provides said desired video output horizontal resolution and said desired video output vertical resolution, and wherein said desired video output horizontal resolution and said desired video output vertical resolution have pixels required for blanking.

21. The apparatus of claim 19, wherein said generating said output horizontal sync frequency comprises:

asserting a horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync start number; and

resetting said horizontal sync pulse when said pixel counter is equivalent to a user programmable horizontal sync end number.

22. The apparatus of claim 19, wherein said generating said output vertical sync frequency comprises:

asserting a vertical sync pulse when said line counter is equivalent to a user programmable vertical sync start number; and

resetting said vertical sync pulse when said line counter is equivalent to a user programmable vertical sync end number, wherein said start number and said end number may be adjusted to cause a phase shift between said input vertical sync pulse and said output vertical pulse.

23. The apparatus of claim 12, wherein said means for generating said first divider value is a system comprising:

a processing unit; and

a memory device.

24. The apparatus of claim 12, wherein said means for generating said output vertical sync frequency is a system comprising:

a processing unit; and

a memory device.

25. The apparatus of claim 12, wherein said first frequency generator is is voltage controlled crystal oscillator.

26. The apparatus of claim 12, wherein said second frequency generator is a voltage controlled oscillator.

27. An apparatus for vertically locking input and output signals comprising:

a continuous input video signal having an input vertical sync frequency;

a micro-controller for generating a first divider value from said continuous input video signal, said first divider value being a positive integer number;

a voltage controlled crystal oscillator for generating a reference frequency, said voltage controlled oscillator having a first adjustable output with a nominal frequency greater than zero, wherein said reference frequency is adjustable by adjusting said first adjustable output of said voltage controlled crystal oscillator about said nominal frequency using an adjustment signal;

a phase locked looped for generating a pixel clock frequency, said phase locked loop generating an error signal by comparing in a phase detector said reference frequency with an intermediate frequency generated by dividing said pixel clock frequency by said first divider value and using said error signal as input to a voltage controlled oscillator to generate said pixel clock frequency;

a computer for generating an output vertical sync frequency from said pixel clock frequency; and

means for generating said adjustment signal from said input vertical sync frequency and said output vertical sync frequency, wherein said adjustment signal is used for adjusting said reference frequency until a lock is obtained between said input vertical sync frequency and said output vertical sync frequency.