High speed bus structure in a multi-port bridge for a local area network
First Claim
1. A multi-port bridge for connecting a plurality of segments of a local area network, the multi-port bridge comprising:
- a. a plurality of ports, each port for interfacing between the multi-port bridge and one of the plurality of segments;
b. a communication bus having a plurality of signal lines, the bus coupled to each of the plurality of ports, wherein data packets are communicated between the ports via the bus and further wherein each packet is received into a receive buffer in the corresponding port and transferred to an assigned location in a memory common to each port; and
a control circuit coupled to the bus, wherein each one of the ports corresponds to one of the signal lines, and further wherein the control circuit applies a selected logic level to an appropriate one of the signal lines to condition a predetermined port to receive a data packet.
1 Assignment
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Accused Products
Abstract
A high speed bus structure for a multi-port bridge for controlling the flow of data packets through the multi-port bridge by using a limited number of bus commands. The bridge includes a memory for storing packets and a plurality of ports. Each port includes a receive buffer, a transmit buffer and a memory pointer buffer. A data packet is received by the receive buffer of a port. As the packet is still being received, a look-up table is utilized to determine which is the appropriate destination port for the packet. The destination ports are notified of their status as destination ports by raising a signal line of the communication bus corresponding to each destination port, referred to as a “bit-map.” If the memory pointer buffer in the destination port is nearly full, the destination port generates a jam request. The source port receives the jam request and, in response, discards the incoming packet and sends a jam signal. If the destination port is available to receive the packet directly from the source port, the destination port receives the packet simultaneously as the packet is stored in the memory device. Once the packet is stored, a memory pointer is placed on the communication bus. The memory pointer is stored in the destination port until the packet can be retrieved from the memory for transmission by the destination port.
137 Citations
48 Claims
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1. A multi-port bridge for connecting a plurality of segments of a local area network, the multi-port bridge comprising:
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a. a plurality of ports, each port for interfacing between the multi-port bridge and one of the plurality of segments;
b. a communication bus having a plurality of signal lines, the bus coupled to each of the plurality of ports, wherein data packets are communicated between the ports via the bus and further wherein each packet is received into a receive buffer in the corresponding port and transferred to an assigned location in a memory common to each port; and
a control circuit coupled to the bus, wherein each one of the ports corresponds to one of the signal lines, and further wherein the control circuit applies a selected logic level to an appropriate one of the signal lines to condition a predetermined port to receive a data packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A multi-port bridge for interconnecting a plurality of segments of a local area network, the multi-port bridge comprising:
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a. a communication bus having a plurality of signal lines;
b. a plurality of ports coupled to the communication bus, each port for receiving data packets from a corresponding segment of the local area network and for transmitting data packets bridged by the multi-port bridge to the corresponding segment, wherein one signal line of the plurality is assigned to each port of the plurality and further wherein each packet is received into a receive buffer in the corresponding port and transferred to an assigned location in a memory common to each port; and
c. a control circuit coupled to the communication bus, wherein the control circuit determines which of the ports are a destination for each packet based upon a destination address contained in the packet wherein the control circuit notifies each port whether the port is a destination for the packet by applying a selected logic level to the signal line of each port, wherein the control circuit notifies each port whether the port is a destination for the packet while the packet is still being received by the multi-port bridge. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of controlling flow of packets in a multi-port bridge having a plurality of ports interconnected to a memory device by a communication bus, the multi-port bridge for interconnecting a plurality of segments of a local area network, the method comprising steps of:
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a. receiving a destination address for a data packet in a source port;
b. determining which one or more of the plurality of ports are a destination port for the packet based upon the destination address;
c. notifying the one or more destination ports of their status as a destination port separate from a step of transmitting a data packet to the destination port;
d. assigning a location in the memory device to the packet;
e. forming indicia of the location;
f. receiving the indicia in the one or more destination ports; and
g. storing the packet at the location. - View Dependent Claims (29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41)
a. transferring the destination address to a control circuit; and
b. comparing the destination address to entries in a table.
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33. The method according to claim 28 wherein the step of notifying comprises steps of:
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a. forming a bit-map for the packet wherein each of the plurality of ports is assigned a respective one signal line of the communication bus, the bit-map including a logic level for each signal line assigned to a port wherein the logic level is indicative of whether the respective port is a destination port for the packet; and
b. placing the bit-map on the communication bus.
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34. The method according to claim 28 wherein the indica includes an identification assigned to the packet and an address in the memory device representative of the location.
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35. The method according to claim 28 wherein the step of storing is performed while the packet is being received by the source port.
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36. The method according to claim 28 further comprising a step of retrieving the packet from the location into at least one of the destination ports for the packet.
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37. The method according to claim 36 wherein at least one of the destination ports for the packet obtains access to the communication bus a first time for initiating the step of retrieving and then releases the communication bus and obtains access to the communication bus a second time for completing the step of retrieving and then releases the communication bus.
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38. The method according to claim 36 further comprising a step of transmitting the packet while the packet is being retrieved from the location.
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39. The method according to claim 28 further comprising a step of receiving the packet from the source port into at least one of the destination ports for the packet while the packet is being stored at the location.
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40. The method according to claim 39 further comprising a step of transmitting the packet while the packet is being received from the source port.
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41. The method according to claim 39 further comprising a step of retrieving the packet from the location into at least one of the destination ports for the packet after the packet has been stored at the location.
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42. A method of controlling flow of packets in a multi-port bridge having a plurality of ports interconnected to a memory device by a communication bus, the multi-port bridge for interconnecting a plurality of segments of a local area network, the method comprising steps of:
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a. receiving a packet having a destination address from a segment associated with a source port for the packet into a receive buffer in the source port;
b. looking-up the destination address in a table for determining one or more destination ports for the packet;
c. assigning a location in the memory device to the packet;
d. forming a bit-map for the packet wherein each of the plurality of ports is assigned a respective one signal line of the communication bus, the bit-map including a logic level for each signal line assigned to a port wherein the logic level is indicative of whether the respective port is a destination port for the packet;
e. placing the bit-map on the communication bus;
f. loading the packet into the memory device at the location in the memory device assigned to the packet; and
g. determining whether each destination port is available to receive the packet and if any destination port is available to receive the packet, performing a step of receiving the packet into a transmit buffer in each available destination port from the source port simultaneously with loading the packet into the memory device. - View Dependent Claims (43, 44, 45, 46, 47, 48)
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Specification