System and method for ESD Protection

• US 6,445,039 B1
• Filed: 01/14/2000
• Issued: 09/03/2002
• Est. Priority Date: 11/12/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kindsfater, Kenneth R., Lu, Fang, Woo, Agnes N.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US09/483,551
• Time in Patent Office: 963 Days
• Field of Search: 257/355, 257/356, 257/357, 257/360
• US Class Current: 257/355
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/0013 with stacked layers
• CPC Class Codes: H01F 2017/0053 with means to reduce eddy currents
• CPC Class Codes: H01F 2021/125 Printed variable inductor with taps, e.g. for VCO
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 27/08 including only semiconductor components of a single kind
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H03B 5/1212 the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
• CPC Class Codes: H03B 5/1228 the amplifier comprising one or more field effect transistors
• CPC Class Codes: H03B 5/1243 the means comprising voltage variable capacitance diodes
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03D 7/161 all the frequency changers being connected in cascade
• CPC Class Codes: H03D 7/18 Modifications of frequency-changers for eliminating image frequencies H03D7/16 takes precedence
• CPC Class Codes: H03G 1/0029 using FETs
• CPC Class Codes: H03H 11/1291 : Current or voltage controlled filters
• CPC Class Codes: H03J 1/0075 : where the receiving frequencies of the stations are stored in a permanent memory, e.g. ROM
• CPC Class Codes: H03J 2200/10 : Tuning of a resonator by means of digitally controlled capacitor bank
• CPC Class Codes: H03J 3/04 : Arrangements for compensating for variations of physical values, e.g. temperature
• CPC Class Codes: H03J 3/08 : by varying a second parameter simultaneously with the tuning, e.g. coupling bandpass filter
• CPC Class Codes: H03J 3/185 : with varactors, i.e. voltage variable reactive diodes
• CPC Class Codes: H03L 7/10 : for assuring initial synchronisation or for broadening the capture range
• CPC Class Codes: H03L 7/23 : with pulse counters or frequency dividers
• CPC Class Codes: H04B 1/28 : the receiver comprising at least one semiconductor device having three or more electrodes

Abstract

An integrated receiver with channel selection and image rejection substantially implemented on a single CMOS integrated circuit is described. A receiver front end provides programmable attenuation and a programmable gain low noise amplifier. Frequency conversion circuitry advantageously uses LC filters integrated onto the substrate in conjunction with image reject mixers to provide sufficient image frequency rejection. Filter tuning and inductor Q compensation over temperature are performed on chip. The filters utilize multi track spiral inductors. The filters are tuned using local oscillators to tune a substitute filter, and frequency scaling during filter component values to those of the filter being tuned. In conjunction with filtering, frequency planning provides additional image rejection. The advantageous choice of local oscillator signal generation methods on chip is by PLL out of band local oscillation and by direct synthesis for in band local oscillator. The VCOs in the PLLs are centered using a control circuit to center the tuning capacitance range. A differential crystal oscillator is advantageously used as a frequency reference. Differential signal transmission is advantageously used throughout the receiver. ESD protection is provided by a pad ring and ESD clamping structure that maintains signal integrity. Also provided are shunts at each pin to discharge ESD build up. The shunts utilize a gate boosting structure to provide sufficient small signal RF performance, and minimal parasitic loading.

Claims

1. An ESD protection system for an integrated circuit that includes a circuit core, a pad ring surrounding the circuit core, and a plurality of bonding pads within the pad ring, the system comprising:

a local power supply bus disposed within the circuit core;

a local ground bus disposed within the circuit core;

an ESD ground bus disposed within the pad ring;

a first ESD clamp coupled between said local ground bus and said ESD ground bus for providing a low impedance discharge path between said local ground bus and said ESD ground bus; and

a second ESD clamp coupled between said local power supply bus and said local ground bus for providing a low impedance discharge path between said local power supply bus and said local ground bus.

2. The ESD protection system of claim 1, wherein said ESD ground bus is disposed between the plurality of bonding pads and an outer edge of the pad ring.

3. The ESD protection system of claim 1, wherein said first ESD clamp comprises a pair of anti-parallel diodes.

4. The ESD protection system of claim 1, wherein said ESD ground bus comprises a partial ring structure that substantially surrounds the circuit core, said structure including a first terminating point and a second terminating point, said first and second terminating points forming a gap for preventing the occurrence of eddy currents.

5. The ESD protection system of claim 1, wherein said ESD ground bus is coupled to one of the plurality of bonding pads for connection to a system ground.

6. The ESD protection system of claim 1, further comprising:

a power supply bus disposed within the pad ring; and

a third ESD clamp coupled between said local power supply bus and said power supply bus.

7. The ESD protection system of claim 6, wherein said power supply bus is disposed between the plurality of bonding pads and an outer edge of the pad ring.

8. The ESD protection system of claim 6, wherein said power supply bus comprises an incomplete ring structure that substantially surrounds the circuit core, said structure including a first terminating point and a second terminating point, said first and second terminating points forming a gap for preventing the occurrence of eddy currents.

9. An ESD protection system for an integrated circuit that includes a circuit core, a pad ring surrounding the circuit core, and a plurality of bonding pads within the pad ring, the system comprising:

a plurality of circuit blocks within the circuit core, each of said plurality of circuit blocks including a local power supply bus and a local ground bus;

an ESD ground bus disposed within the pad ring;

a plurality of first ESD clamps, each of said plurality of first ESD clamps coupling a respective local ground bus within each of said plurality of circuit blocks to said ESD ground bus for providing a low impedance discharge path between each of said local ground busses and said ESD ground bus; and

a plurality of second ESD clamps, each of said plurality of second ESD clamps coupling a respective local power supply bus and a respective local ground bus within each of said plurality of circuit blocks for providing a low impedance discharge path between each local power supply bus and each local ground bus within each of said plurality of circuit blocks.

10. The ESD protection system of claim 9, wherein said ESD ground bus is disposed between the plurality of bonding pads and an outer edge of the pad ring.

11. The ESD protection system of claim 9, wherein each of said plurality of first ESD clamps comprises a pair of anti-parallel diodes.

12. The ESD protection system of claim 9, wherein said ESD ground bus comprises a partial ring structure that substantially surrounds the circuit core, said structure including a first terminating point and a second terminating point, said first and second terminating points forming a ring gap for preventing the occurrence of eddy currents.

13. The ESD protection system of claim 9, wherein said ESD ground bus is coupled to one of the plurality of bonding pads for connection to a system ground.

14. The ESD protection system of claim 9, further comprising:

a power supply bus disposed within the pad ring; and

a plurality of third ESD clamps, each of said plurality of third ESD clamps coupled between a respective local power supply bus within each of said plurality of circuit blocks and said power supply bus.

15. The ESD protection system of claim 14, wherein said power supply bus is disposed between the plurality of bonding pads and an outer edge of the pad ring.

16. The ESD protection system of claim 14, wherein said power supply bus comprises an incomplete ring structure that substantially surrounds the circuit core, said structure including a first terminating point and a second terminating point, said first and second terminating points forming a gap for preventing the occurrence of eddy currents.

17. An ESD protection system for an integrated circuit that includes a circuit core, a pad ring surrounding the circuit core, and a plurality of bonding pads within the pad ring, the system comprising:

a local power supply bus disposed within the circuit core;

a local ground bus disposed within the circuit core;

an ESD ground bus disposed between the plurality of bonding pads and an outer edge of the pad ring;

a first ESD clamp coupled between said local ground bus and said ESD ground bus for providing a low impedance discharge path between said local ground bus and said ESD ground bus; and

a second ESD clamp coupled between said local power supply bus and said local ground bus for providing a low impedance discharge path between said local power supply bus and said local ground bus.

18. The ESD protection system of claim 17, wherein said ESD ground bus comprises a partial ring structure that substantially surrounds the circuit core, said structure including a first terminating point and a second terminating point, said first and second terminating points forming a ring gap for preventing the occurrence of eddy currents.

19. The ESD protection system of claim 17, further comprising:

a power supply bus disposed between the plurality of bonding pads and an outer edge of the pad ring; and

a third ESD clamp coupled between said local power supply bus and said power supply bus.

20. The ESD protection system of claim 19, wherein said power supply bus comprises a partial ring structure that substantially surrounds the circuit core, said structure including a first terminating point and a second terminating point, said first and second terminating points forming a ring gap for preventing the occurrence of eddy currents.