Apparatus and method for partitioned memory protection in cache coherent symmetric multiprocessor systems

• US 6,449,699 B2
• Filed: 03/29/1999
• Issued: 09/10/2002
• Est. Priority Date: 03/29/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Franke, Hubertus, Joseph, Douglas J.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): MCLEAN MAYO, KIMBERLY N
• Application Number:
  US09/277,934
• Publication Number:
  US 20010052054A1
• Time in Patent Office: 1,261 Days
• Field of Search: 711/147, 711/148, 711/152, 711/151, 711/153, 711/154, 711/163, 711/173
• US Class Current: 711/147
• CPC Class Codes: G06F 12/0806 Multiuser, multiprocessor or multiprocessing cache systems
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 12/1458 by checking the subject access rights

Abstract

The present invention provides fault contained memory partitioning in a cache coherent, symmetric shared memory multiprocessor system while enabling fault contained cache coherence domains as well as cache coherent inter partition memory regions. The entire system may be executed as a single coherence domain regardless of partitioning, and the general memory access and cache coherency traffic are distinguished. All memory access is intercepted and processed by the memory controller. Before data is read from or written to memory, the address is verified and the executed operation is aborted if the address is outside the memory regions assigned to the processor in use. Inter cache requests are allowed to pass, though concurrently the accessed memory address is verified in the same manner as the memory requests. During the corresponding inter cache response, a failed validity check for the request results in the stopping of the requesting processor and the repair of the potentially corrupted memory hierarchy of the responding processor.

Claims

1. A method for partitioning memory in a cache coherent symmetric multiprocessor system (SMP) to provide cache coherency for inter cache transfers, the SMP comprising, a plurality of processors each associated with cache memory;

a shared memory;

a shared communications bus; and

a memory controller, said method comprising the following steps;

subdividing said shared memory into a plurality of independent memory partitions and assigning each of said plurality of memory partitions to at least one of said plurality of processors;

executing said plurality of processors in a single cache coherence domain on said shared communications bus;

monitoring inter cache requests for cache lines by requesting processors from responding processors on said shared communications bus of the SMP for detecting if an address associated with an inter cache request for a cache line is outside of a memory partition assigned to a requesting processor; and

correcting a memory partition assigned to a responding processor that responds to the inter cache request with an inter cache transfer of the cache line resulting in an illegal inter cache transfer via a write back of data representing the cache line to the memory partition assigned to the responding processor, wherein each of said plurality of independent memory partitions of said SMP retains independent fault protection properties.

2. The method of claim 1, wherein said shared memory is accessible by each of said plurality of processors via said shared communications bus.

3. The method of claim 2, wherein a memory controller provides partition address maps for specifying valid address ranges of said shared memory that each of said plurality of processors is allowed to access.

4. The method of claim 3, further establishing cache coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

5. The method of claim 4, wherein said inter cache requests are monitored without introducing additional cycles on said shared communications bus.

6. The method of claim 5, wherein each of said inter cache requests is validated against said partition address maps.

7. The method of claim 6, wherein a copy of data associated with the cache line of said inter cache transfer is kept and if said illegal inter cache transfer results said kept data is used to correct said memory partition.

8. The method according to claim 1, wherein the requesting processor is reset after the illegal inter cache transfer.

9. A computer program device readable by a machine, tangibly embodying a program of instructions executable by a machine to perform method steps for partitioning memory in a cache coherent symmetric multiprocessor system (SMP) to provide cache coherency for inter cache transfers comprising a plurality of processors each associated with cache memory;

a shared memory;

a shared communications bus; and

a memory controller, said method comprising the following steps;

subdividing said shared memory into a plurality of independent memory partitions and assigning each of said plurality of independent memory partitions to at least one of said plurality of processors;

executing said plurality of processors in a single cache coherence domain on said shared communications bus;

monitoring inter cache requests for cache lines by requesting processors from responding processors on said shared communications bus of the SMP for detecting if an address associated with an inter cache request for a cache line is outside of a memory partition assigned to a requesting processor; and

correcting a memory partition assigned to a responding processor that responds to the inter cache request with an inter cache transfer of the cache line resulting in an illegal inter cache transfer via a write back of data representing the cache line to the memory partition assigned to the responding processor, wherein each of said plurality of independent memory partitions of said SMP retains independent fault protection properties.

10. The computer program device of claim 9, wherein said shared memory is accessible by each of said plurality of processors via said shared communications bus.

11. The computer program device of claim 10, wherein a memory controller provides partition address maps for specifying valid address ranges of said shared memory that each of said plurality of processors is allowed to access.

12. The computer program device of claim 11, further establishing cache coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

13. The computer program device of claim 12, wherein said inter cache requests are monitored without introducing additional cycles on said shared communications bus.

14. The computer program device of claim 13,wherein each of said inter cache requests is validated against said partition address maps.

15. The computer program device of claim 14, wherein a copy of data associated with the cache line of said inter cache transfer is kept and if said illegal inter cache transfer results said kept data is used to correct said memory partition.

16. The computer program device according to claim 9, wherein the requesting processor is reset after the illegal inter cache transfer.

17. An apparatus for partitioning memory in a cache coherent symmetric multiprocessor system (SMP) to provide cache coherency for inter cache transfers comprising a plurality of processors each associated with cache memory;

a shared memory;

a shared communications bus; and

a memory controller, wherein said processors are executed in a single cache coherence domain, said apparatus comprising;

a means for subdividing said shared memory into a plurality of independent memory partitions and assigning each of said plurality of memory partitions to at least one of said plurality of processors;

a partition manager for monitoring inter cache requests for cache lines by requesting processors from responding processors on said shared communications bus of the SMP to detect if an address associated with an inter cache request is outside of a memory partition assigned to a requesting processor; and

a transaction manager for correcting a memory partition assigned to a responding processor that responds to the inter cache request with an inter cache transfer of the cache line resulting in an illegal inter cache transfer via a write back of data representing the cache line to the memory partition assigned to the responding processor, wherein each of said plurality of independent memory partitions of said SMP retains independent fault protection properties.

18. The apparatus of claim 17, wherein said shared memory is accessible by each of said plurality of processors via said shared communications bus.

19. The apparatus of claim 18, wherein a memory controller provides partition address maps for specifying valid address ranges of said shared memory that each of said plurality of processors is allowed to access.

20. The apparatus of claim 19, further establishing cache coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

21. The apparatus of claim 20, wherein said inter cache requests are monitored without introducing additional cycles on said shared communications bus.

22. The apparatus of claim 21, wherein each of said inter cache requests is validated against said partition address maps.

23. The apparatus of claim 22, wherein a copy of data associated with the cache line of said inter cache transfer is kept and if said illegal inter cache transfer results said kept data is used to correct said memory partition.

24. The apparatus according to claim 17, wherein the requesting processor is reset after the illegal inter cache transfer.

25. An apparatus for controlling partitioned memory in a cache coherent symmetric multiprocessor system (SMP) to provide cache coherency for inter cache transfers, the SMP comprising a plurality of processors each associated with cache memory;

a shared memory;

a shared communications bus;

a data queue; and

a memory controller, said apparatus comprising;

a transaction manager for buffering inter cache requests for cache lines by requesting processors transmitted on the shared communications bus of the SMP;

a partition manager for monitoring the requests for the cache lines on said shared communications bus of the SMP to detect if an address associated with an inter cache request for a cache line is outside of a memory partition assigned to a requesting processor;

a capture buffer for storing a copy of data representing a cache line transferred on said communications bus in response to the inter cache request; and

a multiplexer for correcting a memory partition assigned to a responding processor that responds to the inter cache request with an inter cache transfer of the cache line resulting in an illegal inter cache transfer via a write back of said stored copy of data representing the cache line to said memory partition assigned to the responding processor, wherein each of said plurality of independent memory partitions of said SMP retains independent fault protection properties.

26. The apparatus of claim 25, wherein said shared memory is accessible by each of said plurality of processors via said shared communications bus.

27. The apparatus of claim 26, wherein a memory controller provides partition address maps for specifying valid address ranges of said shared memory that each of said plurality of processors is allowed to access.

28. The apparatus of claim 27, further comprising cache-coherent inter partition shared memory regions for implementing shared locks and other inter-partition communication protocols by allowing overlaps in said partition address maps.

29. The apparatus of claim 28, wherein said inter cache requests are monitored without introducing additional cycles on said shared communications bus.

30. The apparatus of claim 29, wherein each of said inter cache requests is validated against said partition address maps.

31. The apparatus according to claim 25, wherein the requesting processor is reset after the illegal inter cache transfer.