Semiconductor device having SOI structure and manufacturing method thereof

• US 6,452,232 B1
• Filed: 12/01/1999
• Issued: 09/17/2002
• Est. Priority Date: 12/03/1998
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Original Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.)
• Inventors: Adan, Alberto Oscar
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US09/451,843
• Time in Patent Office: 1,021 Days
• Field of Search: 257/61, 257/327, 257/333, 257/337, 257/338, 257/346, 257/347, 257/59, 438/217, 438/276, 438/289, 438/291
• US Class Current: 257/347
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A semiconductor device with a SOI structure comprises; a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film; second conductivity type source and drain regions formed in the surface semiconductor layer; and a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film, wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and which is adjacent to the buried insulating film.

Claims

1. A semiconductor device with a SOI structure comprising:

a SOI substrate having a buried insulating film and a first conductivity type surface semiconductor layer on the buried insulating film;

second conductivity type source and drain regions formed in the surface semiconductor layer;

a gate electrode formed over a first conductivity type channel region between the source and drain regions via a gate insulating film;

impurity diffusion regions of the first conductivity type in the surface semiconductor layer below the source and drain regions;

wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer has a first conductivity type high-concentration impurity diffusion region whose first conductivity type impurity concentration is higher than that in a surface of the channel region and higher than that of the impurity diffusion regions, and wherein the high-concentration impurity diffusion region is adjacent to the buried insulating film.

2. A semiconductor device as claimed in claim 1, in which the first conductivity type high-concentration impurity diffusion region has an impurity concentration of 1×

10¹⁸ atoms/cm³ to 1×

10²⁰ atoms/cm³ and the surface region of the channel region has an impurity concentration of 1×

10¹⁵ atoms/cm³ to 1×

10¹⁸ atoms/cm³.

3. A semiconductor device as claimed in claim 1, in which the channel region is connected to a power source to adjust or vary the characteristics of a transistor.

4. A semiconductor device as claimed in claim 1, in which, in an ON state, a bias voltage is applied to the channel region to reduce the absolute value of a threshold voltage, and in an OFF state, the channel region is set at a floating state to reduce a leakage current.

5. A semiconductor device as claimed in claim 1, in which, in an OFF state, a bias voltage is applied to the channel region to reduce the absolute value of a threshold current, and in an ON state, the channel region is set at a floating state to reduce the threshold voltage.

6. A semiconductor device as claimed in claim 1, in which a surface semiconductor layer between the source and drain regions and the buried insulating film is fully depleted.

7. A semiconductor device as claimed in claim 1, which constitutes a CMOS circuit.

8. A semiconductor device in which the channel region of the semiconductor device as claimed in claim 3 is connected to adjacent channel regions via a high-concentration impurity diffusion region formed under a device isolating region and is connected to a power source at one position.

10. The semiconductor device of claim 1, wherein the first conductivity type high-concentration impurity diffusion region of the channel region does not contact the source or drain regions.

9. A semiconductor device comprising:

a SOI substrate including a buried insulating film, and a first conductivity type surface semiconductor layer on the buried insulating film;

source and drain regions of a second conductivity type, formed in the surface semiconductor layer;

a gate electrode formed over a first conductivity type channel region between the source and drain regions;

at least one impurity diffusion region of the first conductivity type in the surface semiconductor layer below at least one of the source and drain regions;

wherein the source and drain regions are thinner than the surface semiconductor layer, and the channel region in the surface semiconductor layer below the gate electrode includes both (a) a first conductivity type impurity diffusion region adjacent to the buried insulating film, and (b) a surface region at a surface of the channel; and

wherein first conductivity type impurity concentration is higher in (a) than in both (b) and the at least one impurity diffusion region.