Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects

• US 6,455,937 B1
• Filed: 03/17/1999
• Issued: 09/24/2002
• Est. Priority Date: 03/20/1998
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: James A. Cunningham
• Inventors: Cunningham, James A.
• Primary Examiner(s): Cao, Phat X.
• Application Number:
  US09/271,179
• Time in Patent Office: 1,287 Days
• Field of Search: 257/762, 257/760, 257/767, 257/751, 257/763
• US Class Current: 257/762
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/5329 Insulating materials
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

For downwardly-scaled semiconductor processing, high-conductivity metal diffusion is blocked using extremely thin barrier films/layers. Diffusion of a highly-conductive metal is minimized using a dielectric barrier layer positioned a distance under the high-conductivity metal and a distance above the active regions of a semiconductor device. According to one embodiment, a semiconductor device also includes a highly-conductive metal interconnect patterned over a conductive partial diffusion barrier and adhesion promoting film. An underlying dielectric barrier layer against diffusion of the metal interconnect is formed above the active area but not in direct contact with the metal interconnect and is used to block diffusion that is not blocked by the partial diffusion barrier and adhesion promoting film. In a more specific embodiment, the metal interconnect is coated on the upper surface and edges with a thin electrolessly deposited partial barrier film, such as nickel or cobalt.

Claims

1. A semiconductor device comprising:

a substrate;

at least one active region formed in said substrate;

a first dielectric layer over said at least one active region;

a dielectric diffusion barrier layer over said first dielectric layer;

a second dielectric layer over said dielectric diffusion barrier layer;

a metal interconnect over said second dielectric layer; and

a conductive partial-diffusion barrier and adhesion-promoting layer between said metal interconnect and adjacent portions of said second dielectric layer;

said conductive partial-diffusion barrier and adhesion-promoting layer being relatively thin and being spaced from said dielectric diffusion barrier layer by said second dielectric layer.

2. A semiconductor device according to claim 1 wherein said metal interconnect comprises at least one of copper and alloys thereof.

3. A semiconductor device according to claim 1 wherein said metal interconnect comprises at least one of silver and alloys thereof.

4. A semiconductor device according to claim 1 further comprising another dielectric diffusion barrier layer over upper portions of said metal interconnect.

5. A semiconductor device according to claim 1 further comprising another conductive diffusion barrier layer over upper portions of said metal interconnect.

6. A semiconductor device according to claim 1 wherein said conductive partial-diffusion barrier and adhesion-promoting layer has a thickness less than about 20Å

.

7. A semiconductor device according to claim 1 wherein said first and second dielectric layers each comprises silicon dioxide.

8. A semiconductor device according to claim 1 wherein said dielectric diffusion barrier comprises silicon nitride.

9. A semiconductor device according to claim 1 further comprising a conductive plug connecting a lower portion of said metal interconnect to said at least one active region.

10. A semiconductor device according to claim 1 wherein said second dielectric layer has a higher contamination of metal from said metal interconnect than said first dielectric layer.

11. A semiconductor device according to claim 1 wherein said first and second dielectric layers each have a lower dielectric constant than said dielectric diffusion barrier layer.

12. A semiconductor device according to claim 1 wherein said conductive partial-diffusion barrier and adhesion-promoting layer comprises at least one of titanium and titanium nitride.

13. A semiconductor device comprising:

a substrate;

at least one active region formed in said substrate;

a first dielectric layer over said at least one active region;

a dielectric diffusion barrier layer over said first dielectric layer, said dielectric diffusion barrier comprising silicon nitride;

a second dielectric layer over said dielectric diffusion barrier layer;

a metal interconnect over said second dielectric layer, said metal interconnect comprising at least one of copper and alloys thereof;

a conductive partial-diffusion barrier and adhesion-promoting layer between said metal interconnect and adjacent portions of said second dielectric layer;

said conductive partial-diffusion barrier and adhesion-promoting layer being relatively thin and being spaced from said dielectric diffusion barrier layer by said second dielectric layer; and

another diffusion barrier over upper portions of said metal interconnect.

14. A semiconductor device according to claim 13 wherein said conductive partial-diffusion barrier and adhesion-promoting layer has a thickness less than about 20Å

.

15. A semiconductor device according to claim 13 wherein said first and second dielectric layers each comprises silicon dioxide.

16. A semiconductor device according to claim 13 further comprising a conductive plug connecting a lower portion of said metal interconnect to said at-least one active region.

17. A semiconductor device according to claim 13 wherein said second dielectric layer has a higher contamination of metal from said metal interconnect than said first dielectric layer.

18. A semiconductor device according to claim 13 wherein said first and second dielectric layers each have a lower dielectric constant than silicon nitride.

19. A semiconductor device comprising:

a substrate;

at least one active region formed in said substrate;

a dielectric diffusion barrier layer over said at least one active region;

a dielectric layer over said dielectric diffusion barrier layer;

a metal interconnect over said dielectric layer; and

a conductive partial-diffusion barrier and adhesion-promoting layer between said metal interconnect and adjacent portions of said dielectric layer;

said conductive partial-diffusion barrier and adhesion-promoting layer being relatively thin and being spaced from said dielectric diffusion barrier layer by said dielectric layer.

20. A semiconductor device according to claim 19 wherein said metal interconnect comprises at least one of copper and alloys thereof.

21. A semiconductor device according to claim 19 wherein said metal interconnect comprises at least one of silver and alloys thereof.

22. A semiconductor device according to claim 19 further comprising another dielectric diffusion barrier layer over upper portions of said metal interconnect.

23. A semiconductor device according to claim 19 further comprising another conductive diffusion barrier layer over upper portions of said metal interconnect.

24. A semiconductor device according to claim 19 wherein said conductive partial-diffusion barrier and adhesion-promoting layer has a thickness less than about 20Å

.

25. A semiconductor device according to claim 19 wherein said dielectric layer comprises silicon dioxide.

26. A semiconductor device according to claim 19 wherein said dielectric diffusion barrier comprises silicon nitride.

27. A semiconductor device according to claim 19 further comprising a conductive plug connecting a lower portion of said metal interconnect to said at least one active region.

28. A semiconductor device according to claim 19 wherein said dielectric layer has a lower dielectric constant than said dielectric diffusion barrier layer.

29. A semiconductor device according to claim 19 wherein said conductive partial-diffusion barrier and adhesion-promoting layer comprises at least one of titanium and titanium nitride.