Arrangement and method for improved downward scaling of higher conductivity metal-based interconnects

  • US 6,455,937 B1
  • Filed: 03/17/1999
  • Issued: 09/24/2002
  • Est. Priority Date: 03/20/1998
  • Status: Expired due to Term
First Claim
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1. A semiconductor device comprising:

  • a substrate;

    at least one active region formed in said substrate;

    a first dielectric layer over said at least one active region;

    a dielectric diffusion barrier layer over said first dielectric layer;

    a second dielectric layer over said dielectric diffusion barrier layer;

    a metal interconnect over said second dielectric layer; and

    a conductive partial-diffusion barrier and adhesion-promoting layer between said metal interconnect and adjacent portions of said second dielectric layer;

    said conductive partial-diffusion barrier and adhesion-promoting layer being relatively thin and being spaced from said dielectric diffusion barrier layer by said second dielectric layer.

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