Single chip camera device having double sampling operation
DCFirst Claim
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1. A single chip camera device, comprising:
- a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors to read at least one element of the array by first reading a reset level of said at least one element, and subsequently, after an integration time, second reading a charged level of said at least one photoreceptor, said reading and said second reading producing output signals based on both said charged level and said reset level.
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Abstract
A single chip camera device is formed on a single substrate including an image acquisition portion for control portion and the timing circuit formed on the substrate. The timing circuit also controls the photoreceptors in a double sampling mode in which are reset level is first read and then after an integration time a charged level is read.
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18 Claims
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1. A single chip camera device, comprising:
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a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors to read at least one element of the array by first reading a reset level of said at least one element, and subsequently, after an integration time, second reading a charged level of said at least one photoreceptor, said reading and said second reading producing output signals based on both said charged level and said reset level. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 11, 12, 13, 14, 15, 16)
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9. A single chip camera device, comprising:
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a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors to read at least one element of the array by first reading a reset level of said at least one element, and subsequently, after an integration time, second reading a charged level of said at least one photoreceptor, said reading and said second reading producing output signals based on both said charged level and said reset level, further comprising a mode selector device, selecting a mode of operation of said chip wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes. - View Dependent Claims (10)
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17. A method of controlling a single chip camera, comprising:
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integrating, on a single substrate, an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS, said image acquisition portion integrated in said substrate including an array of photoreceptors with output nodes, and a signal controlling device, controlling said photoreceptors and a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;
resetting said output nodes;
sampling a reset value as a first sample;
allowing said photoreceptors to accumulate charge, after resetting said output nodes;
sampling said output nodes after accumulating said charge, producing output signals indicative of a difference between said reset value and said sampled value after accumulating said charge. - View Dependent Claims (18)
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Specification