High speed variable length decoding processor

• US 6,459,391 B1
• Filed: 01/13/2000
• Issued: 10/01/2002
• Est. Priority Date: 01/14/1999
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Yagi, Osamu
• Primary Examiner(s): Jeanpierre, Peguy
• Assistant Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US09/482,704
• Publication Number:
  US 20020084922A1
• Time in Patent Office: 992 Days
• Field of Search: 341/67, 341/65, 341/106, 341/107, 341/61, 382/246, 382/232, 711/214
• US Class Current: 341/67
• CPC Class Codes: H03M 7/40 Conversion to or from variable length codes, e.g. Shannon-Fano code, Huffman code, Morse code
• CPC Class Codes: H04N 19/60 using transform coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A general-purpose processor performs high-speed variable-length decoding. The general-purpose processor includes a video data register for exclusively storing the variable-length code that stores data having a length larger than the maximum length of the variable code to be decoded. The general-purpose processor also includes a data counter register for exclusively storing the length of the data in the video data register which has not been decoded, as well as a pointer register for exclusively storing the address of the variable-length code to be read out next from a bit stream stored in memory. The general-purpose processor also includes an ALU for performing general purpose operations, and decodes the variable-length code stored in the video data register by controlling the video data register, the data counter register, and the pointer register.

Claims

1. In a general purpose processor including a register group comprising a plurality of n-bit registers, a variable length decoding circuit for decoding a variable-length code, the decoding circuit comprising:

a code data register for storing a portion of variable-length coded data, the code data register longer than n-bits and at least as long as a maximum coding length characterizing the variable-length code;

a data count register for storing a data length representing an amount of the portion of variable-length coded data not yet decoded;

a pointer register for storing a memory location from which to next read additional variable-length coded data into the code data register; and

an ALU for decoding the portion of the variable-length coded data in the code data register.

2. The variable length decoding circuit of claim 1, further comprising

a memory for storing variable-length coded data characterized by the maximum coding length.

3. The variable length decoding circuit of claim 1, wherein the code data register exclusively stores portions of the variable-length coded data.

4. The variable length decoding circuit of claim 1, wherein the data count register exclusively stores data lengths representing amounts of the portions of variable-length coded data not yet decoded.

5. The variable length decoding circuit of claim 1, wherein the pointer register exclusively stores positions in memory from which to next read additional variable-length coded data into the code data register.

6. The variable length decoding circuit of claim 1, further comprising a barrel shifter coupled to the ALU.

7. The variable length decoding circuit of claim 6, wherein said ALU includes a logic-OR circuit comprising path transistors.

8. The processor of claim 1, further comprising a cache memory for storing variable-length coded data characterized by the maximum coding length.

9. A processor for decoding a variable-length code characterized by a maximum coding length, the processor comprising:

an instruction fetch section;

an instruction decoder;

a register group comprising a plurality of n-bit general purpose registers;

a code data memory means for storing a portion of variable-length coded data, the code data memory means greater in capacity than n-bits and at least as great in capacity as the maximum coding length;

a data count register for storing a data length representing an amount of the portion of variable-length coded data not yet decoded;

a pointer register for storing a memory location from which to next read additional variable-length coded data into the code data register; and

a decoding means for decoding the portion of the variable-length coded data in the code data register.

10. The processor of claim 9, wherein the pointer register exclusively stores positions in memory from which to next read additional variable-length coded data into the code data register.

11. The processor of claim 9, wherein the data count register exclusively stores data lengths representing amounts of the portions of variable-length coded data not yet decoded.

12. The processor of claim 9, wherein the code data memory means comprises a code data register for exclusively storing portions of the variable-length coded data.

13. In a general purpose processor including a register group comprising a plurality of n-bit registers, a method for variable length decoding, the method comprising:

storing, in a code data register, a portion of variable-length coded data, the code data register longer than n-bits and at least as long as a maximum coding length characterizing the variable-length code;

storing, in a data count register, a data length representing an amount of the portion of variable-length coded data not yet decoded;

storing, in a pointer register, a memory location from which to next read additional variable-length coded data into the code data register; and

decoding the portion of the variable-length coded data in the code data register.

14. A method according to claim 13, wherein storing a data length comprises storing a data length exclusively in the data count register during decoding.

15. A method according to claim 13, wherein storing a memory location comprises storing a memory location exclusively in the pointer register during decoding.

16. A method according to claim 13, wherein decoding includes barrel shifting and performing a logical-OR operation.

17. A method according to claim 13, wherein storing a portion of variable length coded data comprises storing a portion of variable length coded data exclusively in the code data register during decoding.