Massively parallel instruction predecoding
First Claim
Patent Images
1. A microprocessor comprising:
- a prefetch unit configured to receive a plurality of instruction bytes from a main memory subsystem in response to outputting a prefetch address;
a plurality of predecode units coupled to receive a prefetch address and a plurality of instruction bytes from the prefetch unit, wherein each predecode unit is configured to operate on a plurality of instruction bytes independently and in parallel to generate one or more predecode bits per instruction byte; and
a predecode bit correction unit coupled to receive the prefetch address, the instructions bytes from the prefetch unit, and the predecode bits from the plurality of predecode units.
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Abstract
A microprocessor configured to predecode variable length instructions in a massively parallel fashion is disclosed. The microprocessor may comprise a prefetch fetch unit configured to read instruction bytes from memory and a plurality of predecode unit configured to receive and predecode the instruction bytes. The predecode units are configured to operate separately and in parallel to generate one or more predecode bits per instruction byte. The microprocessor may further include a predecode bit correction unit configured to receive, verify, and correct the predecode bits from the parallel predecode units. A computer system and method for predecoding instructions are also disclosed.
43 Citations
20 Claims
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1. A microprocessor comprising:
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a prefetch unit configured to receive a plurality of instruction bytes from a main memory subsystem in response to outputting a prefetch address;
a plurality of predecode units coupled to receive a prefetch address and a plurality of instruction bytes from the prefetch unit, wherein each predecode unit is configured to operate on a plurality of instruction bytes independently and in parallel to generate one or more predecode bits per instruction byte; and
a predecode bit correction unit coupled to receive the prefetch address, the instructions bytes from the prefetch unit, and the predecode bits from the plurality of predecode units. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for predecoding instructions comprising:
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reading a plurality of instruction bytes from a main memory subsystem;
dividing said plurality of instruction bytes into a plurality of subsets;
distributing said subsets among a plurality of predecode units;
processing each subset in the predecode units by;
generating at least one predecode bit for each instruction byte;
outputting the predecode bits to a predecode bit correction unit;
verifying the accuracy of the predecode bits in the predecode bit correction unit; and
correcting any predecode bits that are incorrect. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A computer system comprising:
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a first microprocessor;
a CPU bus coupled to said first microprocessor; and
a modem coupled to said CPU bus, wherein said first microprocessor comprises;
a prefetch unit configured to receive a plurality of instruction bytes from a main memory subsystem in response to outputting a prefetch address;
a plurality of predecode units coupled to receive a prefetch address and a plurality of instruction bytes from the prefetch unit, wherein each predecode unit is configured to operate on a plurality of instruction bytes independently and in parallel to generate one or more predecode bits per instruction byte; and
a predecode bit correction unit coupled to receive the prefetch address, the instructions bytes from the prefetch unit, and the predecode bits from the plurality of predecode units. - View Dependent Claims (18, 19, 20)
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Specification