×

Massively parallel instruction predecoding

  • US 6,460,132 B1
  • Filed: 08/31/1999
  • Issued: 10/01/2002
  • Est. Priority Date: 08/31/1999
  • Status: Expired due to Term
First Claim
Patent Images

1. A microprocessor comprising:

  • a prefetch unit configured to receive a plurality of instruction bytes from a main memory subsystem in response to outputting a prefetch address;

    a plurality of predecode units coupled to receive a prefetch address and a plurality of instruction bytes from the prefetch unit, wherein each predecode unit is configured to operate on a plurality of instruction bytes independently and in parallel to generate one or more predecode bits per instruction byte; and

    a predecode bit correction unit coupled to receive the prefetch address, the instructions bytes from the prefetch unit, and the predecode bits from the plurality of predecode units.

View all claims
  • 5 Assignments
Timeline View
Assignment View
    ×
    ×