Interconnect structure for stacked semiconductor device

• US 6,465,892 B1
• Filed: 04/13/2000
• Issued: 10/15/2002
• Est. Priority Date: 04/13/1999
• Status: Expired due to Term

• Current Assignee: Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), NEC Corporation, Renesas Electronics Corporation, Sony Corporation (Sony Group Corp.), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Fujitsu Limited, Hitachi, Ltd., Sharp Kabushiki Kaisha (Hon Hai Precision Industry Co., Ltd.), Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation), NEC Corporation, OKI Electric Industry Company Limited, Matsushita Electric Corporation (Panasonic Holdings Corporation), Sanyo Electric Company Limited (Panasonic Holdings Corporation), ROHM Co., Ltd., Sony Corporation (Sony Group Corp.), Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Suga, Tadatomo
• Primary Examiner(s): Bowers, Charles
• Assistant Examiner(s): Kielin, Erik J
• Application Number:
  US09/548,916
• Time in Patent Office: 915 Days
• Field of Search: 438/455-459, 438/106-107, 257/753, 257/508, 257/665, 257/685-688, 257/777, 257/782-783, 228/122.1, 228/123.1
• US Class Current: 257/777
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 2224/02125 Reinforcing structures
• CPC Class Codes: H01L 2224/02126 Collar structures
• CPC Class Codes: H01L 2224/05547 comprising a core and a coating
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/08145 the bodies being stacked
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/80357 being flush with the surface
• CPC Class Codes: H01L 2224/80895 between electrically conductive surfaces, e.g. copper-copper direct bonding, surface activated bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/80986 Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01067 : Holmium [Ho]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

In a multi-layer interconnection structure, the wiring length is to be reduced, and the interconnection is to be straightened, at the same time as measures need to be taken against radiation noise. To this end, there is disclosed a semiconductor device in which plural semiconductor substrates, each carrying semiconductor elements, are bonded together. On each semiconductor substrate is deposited an insulating layer through which is formed a connection wiring passed through the insulating layer so as to be connected to the interconnection layer of the semiconductor element. On a junction surface of at least one of the semiconductor substrates is formed an electrically conductive layer of an electrically conductive material in which an opening is bored in association with the connection wiring. The semiconductor substrates are bonded together by the solid state bonding technique to interconnect the connection wirings formed on each semiconductor substrate.

Claims

1. A semiconductor device comprising:

a plurality of semiconductor substrates, wherein

a wiring layer is formed on each semiconductor substrate;

an insulating layer is deposited on each semiconductor substrate,

a connection wiring passes through said insulating layer for connection to said wiring layer on each semiconductor substrate; and

an electrically conductive layer comprised of an electrically conductive material having an opening formed by patterning in register with said connection wiring is formed on a junction surface of at least one of said semiconductor substrates, said electrically conductive layer operating as either a grounding layer or a power source layer;

and wherein said semiconductor substrates are bonded together to interconnect the connection wirings formed on each semiconductor substrate.

2. The semiconductor device according to claim 1 wherein

said semiconductor substrates are bonded together by a solid state bonding technique.

3. The semiconductor device according to claim 1 further comprising:

an electrically conductive layer formed on a junction surface of each of paired semiconductor substrates to be bonded together,

metal materials constituting these electrically conductive layers bonded together.

4. The semiconductor device according to claim 1, further comprising:

an electrically conductive layer formed on a junction surface of one of paired semiconductor substrates to be bonded together,

the electrically conductive layer and an insulating layer of an opposite side semiconductor substrate being bonded together.

5. The semiconductor device according to claim 4, further comprising

an electrically conductive layer deposited between two insulating layers.

6. The semiconductor device according to claim 1

wherein

an inner diameter of the opening formed in said electrically conductive layer is larger than an inner diameter of an opening formed in said insulating layer.

7. The semiconductor device according to claim 6

wherein

the connection wirings connected to each other on the junction surface are insulated from the electrically conductive layer by embedding an insulating material in an opening provided in said electrically conductive layer.

8. A semiconductor device comprising:

a plurality of semiconductor substrates, wherein

a wiring layer is formed on each semiconductor substrate;

an insulating layer is deposited on each semiconductor substrate,

a connection wiring passes through said insulating layer for connection to said wiring layer on each semiconductor substrate; and

an electrically conductive layer comprised of an electrically conductive material having an opening formed by patterning in register with said connection wiring is formed on a junction surface of at least one of said semiconductor substrates;

and wherein the electrically conductive layer on said junction surface of at least one said semiconductor substrate is bonded to an insulating layer of an opposite side semiconductor substrate in a manner to interconnect the connection wirings formed on each semiconductor substrate.

9. The semiconductor device of claim 8 wherein said semiconductor substrates are bonded together by a solid state bonding technique.

10. The semiconductor device according to claim 8 further comprising an electrically conductive layer deposited between two insulating layers.

11. The semiconductor device according to claim 8 wherein the inner diameter of the opening formed in said electrically conductive layer is larger than an inner diameter opening formed in said insulating layer.