Fault tolerant data communication network

• US 6,467,003 B1
• Filed: 12/02/1999
• Issued: 10/15/2002
• Est. Priority Date: 01/21/1997
• Status: Expired due to Fees

• Current Assignee: Alliedsignal Icn.
• Original Assignee: Honeywell International Inc.
• Inventors: Doerenberg, Frank M. G., Topic, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/454,054
• Time in Patent Office: 1,048 Days
• Field of Search: 710/117, 710/124, 710/305, 710/45, 370/60
• US Class Current: 710/117
• CPC Class Codes: G05D 1/0077 using redundant signals or controls

Abstract

The present invention provides a fault tolerant bus architecture and protocol for use in an Integrated Hazard Avoidance System of the type generally used in avionics applications. In addition, the present invention may also be used in applications, aviation and otherwise, wherein data is to be handled with a high degree of integrity and in a fault tolerant manner. Such applications may include for example, the banking industry or other safety critical processing functions, including but not limited to environmental control.

Claims

1. A data bus system comprising:

a data bus including a data line for transmitting data in a plurality of time frames, each of said time frames divided into a plurality of time slots;

a processor having a corresponding application memory, said processor formulating a message for transmission on said data bus during one of said time slots;

a transmitter coupling said processor to said data line; and

an arbitration circuit operatively coupled to said transmitter and said processor, said arbitration circuit generating a first signal enabling said transmitter and generating a second signal informing said processor of said enabling of said transmitter.

2. The data bus system recited in claim 1, wherein said arbitration circuit further determines an occurrence of said time slot and generates said first and second signals responsively to said occurrence.

3. The data bus system recited in claim 2, wherein said occurrence of said time slot is determined by a processor identification function.

4. The data bus system recited in claim 2, further comprising a table operatively coupled to said arbitration circuit for determining said occurrence of said time slot.

5. The data bus system recited in claim 4, further comprising a clock operatively coupled to said arbitration circuit.

6. The data bus system recited in claim 2, wherein:

said time slot is a first unique one of a plurality of time slots; and

said processor comprises a first processor, said transmitter comprises a first transmitter, said arbitration circuit comprises a first arbitration circuit, and together said first processor, said first transmitter, and said first arbitration circuit comprise a first processing node; and

further comprising

a second processing node comprising;

a second processor having a corresponding application memory, said second processor formulating a message for transmission on said data bus during a second unique one of said time slots;

a second transmitter coupling said second processor to said data line; and

a second arbitration circuit operatively coupled to said second transmitter and said second processor, said second arbitration circuit determining an occurrence of said second unique one of said time slots and responsively generating both a first signal enabling said second transmitter and a second signal informing said second processor of said enabling of said second transmitter.

7. The data bus system recited in claim 6, wherein said second arbitration circuit of said second processing node is synchronized with said first arbitration circuit of said first processing node.

8. The data bus system recited in claim 6, wherein:

said data line is one of a plurality of data lines;

said first processor formulates multiple ones of said message for transmission on different ones of said data lines;

said first transmitter is one of a plurality of first transmitters, each of said first transmitters coupling said first processor to a different one of said data lines;

said first arbitration circuit is one of a plurality of first arbitration circuits, each of said first arbitration circuits coupled to said first processor and to different ones of said first transmitters and generating said first signal enabling a corresponding one of said first transmitters and generating said second signal informing said first processor of said enabling of said corresponding first transmitter;

said second processor formulates multiple ones of said message for transmission on different ones of said data lines;

said second transmitter is one of a plurality of second transmitters, each of said second transmitters coupling said second processor to a different one of said data lines;

said second arbitration circuit is one of a plurality of second arbitration circuits, each of said second arbitration circuits coupled to said second processor and to different ones of said second transmitters and generating said first signal enabling a corresponding one of said second transmitters and generating said second signal informing said second processor of said enabling of said corresponding second transmitter.

9. The data bus system recited in claim 8, wherein each said first and second arbitration circuits further determines an occurrence of said time slot on a corresponding one of said data lines.

10. The data bus system recited in claim 9, wherein:

each said first arbitration circuits enables one of said first transmitters corresponding to a different one of said first arbitration circuits; and

each said second arbitration circuits enables one of said second transmitters

corresponding to a different one of said second arbitration circuits.

11. The data bus system recited in claim 10, wherein ones of said second transmitters couple said second processor to identical ones of data lines as ones of said first transmitters couple said first processor.

12. The data bus system recited in claim 11, wherein:

each said first arbitration circuit coordinates with each other of said first arbitration circuits to generate each of said first and second signals; and

each said second arbitration circuit coordinates with each other of said second arbitration circuits to generate each of said first and second signals.

13. The data bus system recited in claim 12, wherein at least one of said first arbitration circuits coordinates with at least one of said second arbitration circuits to determine a position of said first unique one of a plurality of time slots.

14. The data bus system recited in claim 1, wherein:

said data line is one of a plurality of data lines;

said processor formulates said message for transmission on two or more of said data lines;

said transmitter is one of a plurality of transmitters, each of said transmitters coupling said processor to a different one of said data lines; and

said arbitration circuit is one of a plurality of arbitration circuits, each of said arbitration circuits coupled to said processor and to different ones of said transmitters and generating said first signal enabling a corresponding one of said transmitters and generating said second signal informing said processor of said enabling of said corresponding transmitter.

15. The data bus system recited in claim 14, wherein each said arbitration circuit further determines an occurrence of said time slot on a corresponding one of said data lines.

16. The data bus system recited in claim 15, further comprising a table operatively coupled to said arbitration circuits for determining said occurrence of each said time slot.

17. The data bus system recited in claim 16, wherein said table is one of a plurality of tables, one of said tables operatively coupled to different ones of said arbitration circuits.

18. The data bus system recited in claim 15, further comprising a clock operatively coupled to each of said arbitration circuits.

19. The data bus system recited in claim 18, wherein said clock is one of a plurality of independent clocks, ones of said clocks operatively coupled to different ones of said arbitration circuits.

20. The data bus system recited in claim 15, wherein each said arbitration circuit enables one of said transmitters corresponding to a different one of said arbitration circuits.

21. The data bus system recited in claim 20, wherein each said arbitration circuit coordinates with each other of said arbitration circuits to generate each of said first and second signals.

22. The data bus system recited in claim 15, wherein:

said processor is one of a plurality of processors, each said processor having a corresponding application memory and formulating a message for transmission on said data bus during one of said time slots;

each of said transmitters couple a different one of said processors to a different one of said data lines; and

each of said arbitration circuits is coupled to a different one of said processors and to a different one of said transmitters, each of said arbitration circuits generating both said first signal enabling a corresponding one of said transmitters and said second signal informing a corresponding one of said processors of said enabling of said corresponding one of said transmitters.

23. The data bus system recited in claim 22, wherein each of said processors cooperate during time periods selected for dual sourced operations and independently and concurrently run different applications during other time periods.

24. A data bus system comprising:

a data bus including a plurality of data lines for transmitting data in a plurality of time frames divided into a plurality of discrete time slots;

a plurality of processing nodes, each said processing node further comprising a processor for executing one or more application programs;

an application memory coupled to said processor, said application memory storing data resulting from said programs;

a pair of transmitters individually coupled to said application memory and to one or more data lines for transmitting said data to said data bus;

a time table for mapping said time slots in each of said frames into a data transmission channel wherein each of said channels is assigned to a predetermined one of said processing nodes for transmission of data from said application memory through each of said transmitters to said channel on said data lines;

a pair of interconnected arbitration circuits individually coupled to said time table and to said application memory and to a different one of said pair of transmitters, in response to said time table each said arbitration circuit individually enabling one of said transmitters and informing said processor of said enabling of said transmitter.

25. The system recited in claim 24, wherein each said arbitration circuit enables a one of said transmitters associated with an other of said arbitration circuits.

26. The system recited in claim 25, wherein said time table is one of a plurality of time tables and each arbitration circuit is coupled to a different one of said time tables.

27. The data bus system recited in claim 24, wherein each said arbitration circuit associated with one of said processing nodes is synchronized with each other of said arbitration circuits associated with said one of said processing nodes.

28. The data bus system recited in claim 24, wherein at least one of said arbitration circuits of a first one of said processing nodes coordinates with at least one of said arbitration circuits of a second one of said processing nodes.

29. The data bus system recited in claim 28, wherein said arbitration circuit of said first processing node is synchronized with said arbitration circuit of said second processing node.

30. Th e data bus system recited in claim 29, wherein each said arbitration circuit is further operatively coupled to an independent clock.

31. A protocol for placing data from a plurality of processing nodes on a data bus, the protocol comprising:

allocating to each of the plurality of processing nodes a predetermined number of time slots on a data bus in which to transmit data messages;

formulating a plurality of identical data messages in a processor associated with one of said processing nodes;

performing a plurality of independent determinations of an occurrence of one of said allocated time slots;

enabling a plurality of couplings between said processor and said data bus in response to a plurality of positive ones of said determinations of said occurrence of one of said allocated time slots;

informing said processor of said occurrence of one of said allocated time slots in response to said plurality of positive ones of said determinations; and

placing said plurality of identical data messages on said data bus.

32. The protocol recited in claim 31, wherein said enabling further comprises a first enabling function acting on a coupling function associated with a second enabling function and a second enabling function acting on a coupling function associated with said first enabling function.

33. The protocol recited in claim 32, wherein said performing a plurality of independent determinations of an occurrence of one of said allocated time slots is associated with retrieving data defining said allocating.