System of accessing data in a graphics system and method thereof

• US 6,469,703 B1
• Filed: 07/02/1999
• Issued: 10/22/2002
• Est. Priority Date: 07/02/1999
• Status: Expired due to Term

• Current Assignee: Vantage Micro LLC (Fullbrite Capital Partners, LLC)
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Aleksic, Milivoje, Li, Raymond M., Cheng, Danny H. M., Mizuyabu, Carl K., Asaro, Antonio
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/347,202
• Time in Patent Office: 1,208 Days
• Field of Search: 345/541, 345/542, 345/544, 345/531, 345/536, 345/422, 345/530, 345/501, 345/564, 345/419
• US Class Current: 345/542
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A central processor unit (CPU) is connected to a system/graphics controller generally comprising a monolithic semiconductor device. The system/graphics controller is connected to an input output (IO) controller via a high-speed PCI bus. The IO controller interfaces to the system graphics controller via the high-speed PCI bus. The IO controller includes a lower speed PCI port controlled by an arbiter within the IO controller. Generally, the low speed PCI arbiter of the IO controller will interface to standard 33 MHz PCI cards. In addition, the 10 controller interfaces to an external storage device, such as a hard drive, via either a standard or a proprietary bus protocol. A unified system/graphics memory which is accessed by the system/graphics controller. The unified memory contains both system data and graphics data. In a specific embodiment, two channels, CH0 and CH1 access the unified memory. Each channel is capable of accessing a portion of memory containing graphics data or a portion of memory containing system data. Therefore, it is possible for each channel to access graphics data simultaneously, system data simultaneously, or graphics and system data simultaneously. Simultaneous accesses are facilitated by assuring the physical addresses are partitioned into blocks within the unified memory, such blocks of data are adjacent blocks are accessed by different channels.

Claims

1. A method of accessing data in a data processing system having a graphics engine, the method comprising:

accessing a first portion of a frame of graphics data through a first channel of memory;

accessing a second portion of a frame of graphics data through a second channel of memory;

accessing system data through the first channel of memory simultaneously with the step of accessing the second portion of a frame of graphics data through the second channel of memory.

2. The method of claim 1, wherein the first portion and second portion are logically consecutive blocks of graphics data.

3. The method of claim 2, wherein the logically consecutive blocks are for storing horizontally adjacent pixel matrices.

4. The method of claim 2, wherein the logically consecutive blocks are for storing vertical adjacent pixel matrices.

5. The method of claim 1, wherein the first channel accesses data on first clock edge, and the second channel accesses data on a second clock edge, wherein the first clock edge and the second clock edge are skewed from one another.

6. The method of claim 1, wherein:

the step of accessing the first portion of a frame of graphics data through a first channel includes the first portion being a first type of graphics memory;

the step of accessing a second portion of a frame of graphics data through a second channel includes the second portion being a second type of graphics memory.

7. The method of claim 6, wherein the step of accessing the first portion and the step of accessing a second portion are performed substantially simultaneously.

8. The method of claim 6, wherein the first portion of a frame of graphics data and the second portion of a frame of graphics data are associated with a common pixel.

9. The method of claim 6, wherein the first type is z graphics data, and the second type is destination graphics data.

10. A method of partitioning memory in a data processing system, the method comprising:

identifying a first portion of a memory associated with a first channel as graphics memory;

identifying a second portion of a memory associated with a second channel as graphics memory;

partitioning each of the first and a second portion of memory into blocks;

mapping each of the blocks to an X-Y location, wherein each block associated with a first channel is horizontally and vertically adjacent to blocks associated with the second channel.

11. A method of accessing data in a data processing system, the method comprising the steps of:

storing a first data to one of a first memory and a second memory, wherein the first memory is associated with a first memory channel, the second memory is associated with a second memory channel, and the first data is associated with a first location of a video image and has a first video data type,

storing a second data to one of the first and second memory, wherein the second data is associated with the first location of the video image and has a second video data type, and is stored in a different memory than the first data.

12. The method of claim 11, wherein the first data type is a Z-data associated with a three-dimensional image.

13. The method of claim 12, wherein the second data type is a destination (DST) data associated with a three-dimensional image.

14. The method of claim 11, further comprising the steps of:

storing a third data to one of the first and second memory, wherein the third data is associated with a second location of a video image, has the first video data type, and is stored in a different memory that the first data,

storing a fourth data to one of the first and second memory, wherein the second data is associated with the second location of the video image, has the second video data type, and is stored in a different memory than the third data.

15. A method of partitioning data, the method comprising:

determining the memory present in a system;

partitioning the memory between a first channel and a second channel;

partitioning a first portion of the memory associated with the first channel as system memory;

partitioning a second portion of the memory associated with the first channel as graphics memory; and

partitioning at least a portion of the memory associated with the second channel as graphics memory.

16. The method of claim 15, wherein the graphics memory associated with the first channel and the graphics memory associated with the second channel are arranged in blocks of data having adjacent physical addresses.

17. The method of claim 16, wherein the adjacent physical addresses are arranged in rows and columns so that each block associated with a row and column is adjacent to a block accessed by a different channel.