Low-level circuit implementation of signal flow graphs for real-time signal processing of high-speed digital signals

• US 6,469,988 B1
• Filed: 07/08/1999
• Issued: 10/22/2002
• Est. Priority Date: 07/08/1999
• Status: Expired due to Term

• Current Assignee: MACOM Technology Solutions Holdings, Inc.
• Original Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Inventors: Ke, Yang Jing, Yang, Kewei, Lin, Feng Cheng
• Primary Examiner(s): Mai, Tan V.
• Application Number:
  US09/349,832
• Time in Patent Office: 1,202 Days
• Field of Search: 370/289, 370/282, 370/286, 370/290, 370/294, 370/296, 375/220, 375/346, 379/412
• US Class Current: 370/289
• CPC Class Codes: H04L 25/0264 Arrangements for coupling to transmission lines duplexing arrangements H04L5/14; line equalisers, line build-out devices H04L25/03878
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex

Abstract

Signal processing techniques are applied to data rates at state-of-the-art circuit speeds (presently 1.6 Gbit/sec) by carrying out the signal flow graph of a cannonical FIR filter algorithm using hybrid analog and digital circuit techniques. A plurality of digital to analog converters (DACs) generate analog currents that are the analogue of the tap coefficients of the FIR filter model. The DACs are used as programmable current sources for the tail current sources of respective differential pair stages. Differential delay signals that are the analogue of the FIR delay-line tap signals are connected to the inputs of respective ones of the differential pair stages. The drains of the input devices of the differential pair stages are connected in parallel to common complementary load circuits. The delay signals act to steer the tap coefficient currents to one or the other of the common load circuits. The parallel connection to common load circuits acts to sum the currents sunk (if any) by each of the commonly connected input devices. This current summation is the analogue of the FIR accumulator. Because the tap coefficient currents are readily programmable, the filter may be adaptive. An illustrative embodiment uses the invention in a transceiver for high-speed full-duplex (bi-directional simultaneous) signaling over a single channel interconnect. An adaptation algorithm is used at system initialization to train the tap coefficients according to the particular channel characteristics. The invention enables reliable extraction of receive-signals from the inherent ringing induced by the channel interconnect and at higher data rates than previously possible.

Claims

1. A chip-to-chip interface comprising:

a connection coupling a first chip to a second chip;

in the first chip, a first transceiver configured to transfer a first signal to the second chip over the connection and receive a second signal from the second chip over the connection, and process the first signal to predict first signal echo and remove the predicted first signal echo from the second signal; and

in the second chip, a second transceiver configured to transfer the second signal to the first chip over the connection and receive the first signal from the first chip over the connection, and process the second signal to predict second signal echo and remove the predicted second signal echo from the first signal.

2. The chip-to-chip interface of claim 1 wherein the first signal and the second signal form a full-duplex signal on the connection, and:

the first transceiver is configured to remove the first signal and the predicted first signal echo from the full-duplex signal; and

the second transceiver is configured to remove the second signal and the predicted second signal echo from the full-duplex signal.

3. The chip-to-chip interface of claim 1 wherein:

the first transceiver includes a first filter configured to process the first signal to predict the first signal echo based on first tap coefficients and is configured to adaptively set the first tap coefficients during an initialization process when the first transceiver is transmitting a test signal and the second transceiver is not transmitting; and

the second transceiver includes a second filter configured to process the second signal to predict the second signal echo based on second tap coefficients and is configured to adaptively set the second tap coefficients during the initialization process when the second transceiver is transmitting the test signal and the first transceiver is not transmitting.

4. The chip-to-chip interface of claim 3 wherein first transceiver and the second transceiver are configured to initiate the initiation process in response to power-up.

5. A method of operating a chip-to-chip interface where a connection couples a first chip to a second chip, the method comprising;

in the first chip, transferring a first signal to the second chip over the connection and receiving a second signal from the second chip over the connection, and processing the first signal to predict first signal echo and removing the predicted first signal echo from the second signal; and

in the second chip, transferring the second signal to the first chip over the connection and receiving the first signal from the first chip over the connection, and processing the second signal to predict second signal echo and removing the predicted second signal echo from the first signal.

6. The method of claim 5 wherein the first signal and the second signal form a full-duplex signal on the connection, and:

in the first chip, removing the predicted first signal echo from the second signal comprises removing the predicted first signal echo from the full-duplex signal, and further comprising removing the first signal from the full-duplex signal; and

in the second chip, removing the predicted second signal echo from the first signal comprises removing the predicted second signal echo from the full-duplex signal, and further comprising removing the second signal from the full-duplex signal.

7. The method of claim 5 wherein:

processing the first signal to predict the first signal echo comprises using a first filter to process the first signal based on first tap coefficients and further comprising adaptively setting the first tap coefficients during an initialization process when the first transceiver is transmitting a test signal and the second transceiver is not transmitting; and

processing the second signal to predict the second signal echo comprises using a second filter to process the second signal based on second tap coefficients and further comprising adaptively setting the second tap coefficients during the initialization process when the second transceiver is transmitting the test signal and the first transceiver is not transmitting.

8. The method of claim 7 further comprising initiating the initiation process in response to power-up.

9. A transceiver for a first chip that is coupled to a second chip by a connection wherein the first chip is configured to transfer a first signal to the second chip over the connection, the second chip is configured to transfer a second signal to the first chip over the connection, and the first signal and the second signal form a full-duplex signal on the connection, the transceiver comprising:

a driver configured to generate the first signal;

circuitry configured to process the first signal to predict first signal echo and remove the first signal and the predicted first signal echo from the full-duplex signal to obtain the second signal.

10. The transceiver of claim 9 wherein the circuitry comprises:

delay circuitry configured to generate a plurality of delayed first signals;

digital-to-analog conversion circuitry configured to process the first signal and the delayed first signals to generate a predictive signal comprising the first signal and the predicted first signal echo; and

summation circuitry configured to remove the predictive signal from the full-duplex signal to obtain the second signal.

11. The transceiver of claim 9 wherein the circuitry includes a filter configured to process the first signal based on tap coefficients to predict the first signal echo, and the circuitry is configured to adaptively set the first tap coefficients during an initialization process when the first chip is transmitting a test signal and the second chip is not transmitting.

12. The transceiver of claim 11 wherein the circuitry is configured to initiate the initiation process in response to power-up.

13. A method of operating a transceiver for a first chip that is coupled to a second chip by a connection wherein the first chip transfers a first signal to the second chip over the connection, the second chip transfers a second signal to the first chip over the connection, and the first signal and the second signal form a full-duplex signal on the connection, the transceiver comprising:

processing the first signal to predict first signal echo; and

removing the first signal and the predicted first signal echo from the full-duplex signal to obtain the second signal.

14. The method of claim 13 wherein processing the first signal to predict the first signal echo and removing the first signal and the predicted first signal echo from the full-duplex signal comprises:

generating a plurality of delayed first signals;

processing the first signal and the delayed first signals to generate a predictive signal comprising the first signal and the predicted first signal echo; and

removing the predictive signal from the full-duplex signal to obtain the second signal.

15. The method of claim 13 wherein processing the first signal to predict the first signal echo comprises using filter configured to process the first signal based on tap coefficients to predict the first signal echo, and further comprising adaptively setting the first tap coefficients during an initialization process when the first chip is transmitting a test signal and the second chip is not transmitting.

16. The method of claim 15 further comprising initiating the initiation process in response to power-up.