Pixel sensor column amplifier architecture
First Claim
1. A pixel column sensor for creating a reduced noise differential image signal comprising:
- a first and a second double sampling (DS) circuit, each having a first and a second sample period;
the first DS circuit having an input coupled to an image signal that is subject to a set of noise components, an output outputting a first side of the reduced noise differential image signal, and a reference input;
the second DS circuit having an input coupled to a reference image signal that is held in a reset state and is subject to the set of noise components, an output outputting a second side of the reduced noise differential image signal, and a reference input;
a reference voltage source coupled to the reference inputs of the first and second DS circuits; and
wherein the reference voltage is sampled during the first sample time period in the first and second DS circuits.
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Abstract
A pixel column amplifier architecture creates a reduced noise differential image signal from an pixel sensor array. The pixel column amplifier architecture comprises a first double sampling (DS) circuit and a second DS circuit that has the same configuration as the first DS circuit. An image signal containing a combination of noise components created on a substrate is coupled to the first DS circuit. A reference image signal, held in a reset state, represents the noise component of the image signal and is coupled to the second DS circuit. Further, a reference voltage source is coupled to a reference input of both the first DS and the second DS circuits. The first DS circuit provides the first side of the differential image signal, and the second DS circuit provides the second side of the differential image signal.
148 Citations
16 Claims
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1. A pixel column sensor for creating a reduced noise differential image signal comprising:
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a first and a second double sampling (DS) circuit, each having a first and a second sample period;
the first DS circuit having an input coupled to an image signal that is subject to a set of noise components, an output outputting a first side of the reduced noise differential image signal, and a reference input;
the second DS circuit having an input coupled to a reference image signal that is held in a reset state and is subject to the set of noise components, an output outputting a second side of the reduced noise differential image signal, and a reference input;
a reference voltage source coupled to the reference inputs of the first and second DS circuits; and
wherein the reference voltage is sampled during the first sample time period in the first and second DS circuits.
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2. A pixel column amplifier architecture for creating a reduced noise differential image signal, comprising:
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a first double sampling (DS) circuit having an input coupled to an image signal that is subject to a set of noise components, an output outputting a first side of the reduced noise differential image signal, and a reference input;
a second DS circuit having an input coupled to a reference image signal that is subject to the set of noise components and is held in a reset state, an output outputting a second side of the reduced noise differential image signal, and a reference input;
a reference voltage source coupled to the reference inputs of the first and second DS circuits; and
wherein one of the first and second DS circuits further includes, a first sample hold circuit having an input coupled to the input of the one DS circuit, an output, and a control input, a first subtract circuit having a plus input coupled to the output of the first sample hold circuit, a minus input coupled to the input of the one DS circuit and the input of first sample hold circuit, and an output, an amplifier having offset cancellation, having an input coupled to the output of the first subtract circuit, an output, and a gain setting controlled by capacitor area ratios, a second sample hold circuit having an input coupled to the reference input of the one DS circuit, an output, and a control signal coupled to said control signal of first sample hold circuit, a second subtract circuit having a plus input coupled to the input of the second sample hold circuit, a minus input coupled to the output of said amplifier, and an output, a third sample hold circuit having an input coupled to the output of the second subtract circuit, an output coupled to said output of said one DS circuit, and a control signal, a first control signal coupled to said control inputs of first and second sample hold circuits, and a second control signal coupled to the control input of the third sample hold circuit.
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3. A pixel column amplifier architecture for creating a reduced noise differential image signal, comprising:
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a first double sampling (DS) circuit having an input coupled to an image signal that is subject to a set of noise components, an output outputting a first side of the reduced noise differential image signal, and a reference input;
a second DS circuit having an input coupled to a reference image signal that is subject to the set of noise components and is held in a reset state, an output outputting a second side of the reduced noise differential image signal, and a reference output; and
a reference voltage source coupled to the reference inputs of the first and second DS circuits; and
wherein one of the first and second DS circuits includes, a first, a second, a third, and a fourth switch, each having an input, a control input, and an output, a first storage element having a first node coupled to output of said first switch and a second node, an amplifier having an input coupled to the second node of the first storage element and the input of the second switch, an output coupled to the output of the second switch and the input of the third switch coupled to the output of the one DS circuit, and a gain setting, a second storage element having a first node coupled to the second node of the first storage element and the input of said amplifier and a second node connected to the inputs of the third and fourth switch, the fourth switch having an input coupled to the reference input of said one DS circuit; a first control signal coupled to said control input of said first switch;
a second control signal coupled to said control inputs of the second and fourth switch; and
a third control signal coupled to said control input of said third switch.
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4. An imaging system for generating an essentially parasitic noise free differential image signal based on an image focused on the imaging system, comprising:
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a plurality of active pixel sensors arranged in an array of rows and columns to form a sensor array, each active pixel sensor able to generate a voltage potential at a diffusion node corresponding to detected light intensity by said active pixel sensor or a reset signal, each active pixel sensor buffering said voltage potential present on the diffusion node from other signals generated external to said active pixel sensor;
a plurality of reference pixel sensors, arranged in an array of rows and at least one column, thereby forming at least one reference column signal, said reference pixel sensors essentially having the same configuration as said active pixel sensors but having a reference reset signal to generate a voltage potential at a diffusion node, each reference pixel sensor buffering said reset potential present on the diffusion node from other signals generated external to said reference pixel sensor;
a reference voltage source;
a plurality of active pixel column amplifier circuits, each respective amplifier circuit being connected to the respective active pixel sensors in a column forming a respective column signal, said respective column signal subject to a combination of noise sources, each active pixel column amplifier circuit further comprising, a first double sampling (DDS) circuit having an input, an output, and a reference input, said input of the first DS circuit coupled to said respective column signal, and said reference voltage source coupled to said reference input of each said first DS circuit;
at least one reference column amplifier circuit, said at least one reference column amplifier coupled to a respective said reference column signal held in a reset state, said respective reference column signal subject to a combination of noise sources as said respective active pixel columns, said respective reference column amplifier circuit further comprising, a second DS circuit having essentially the same configuration as said first DS circuit, said second DS circuit having an input, an output, and a reference input, said input of second DS circuit coupled to said respective reference column signal held in a reset state, and said reference input of each said second DS circuit coupled to said reference voltage source; and
a timing controller coupled to each said active pixel column amplifier and each reference column amplifier circuits, wherein the timing controller activates said plurality of active pixel sensors to provide a voltage signal corresponding to a present frame to the active pixel column amplifier and to provide a non-reset signal to the activated reference pixel sensor to provide a voltage signal corresponding to a reset level to the respective reference column amplifier circuits, and then to provide a voltage signal corresponding to a reset signal to the active pixel column amplifier circuits and said non-reset signal to the reference column amplifier circuits, and wherein the timing controller enables the active pixel column amplifier circuits to sequentially provide each said column amplifier circuit output signal to a first common output line and wherein the timing controller enables the reference column amplifier output signal to a second common output line to generate the imaging system parasitic noise free differential signal. - View Dependent Claims (5, 6, 7, 8, 9, 10, 11, 12, 13)
a first sample hold circuit having an input, an output, a control input, said input coupled to said input of each respective DS circuit;
a first subtract circuit having a plus input, a minus input and an output, said minus input coupled to said input of each said respective DS circuit and said input of first sample hold circuit, said plus input coupled to said output of said first sample hold circuit;
an amplifier having offset cancellation, having an input, an output, and a gain setting, said gain setting controlled by capacitor area ratios, said input coupled to said output of first subtract circuit;
a second sample hold circuit having an input, an output, and a control signal, said input coupled to said reference input of each respective DS circuit, said control signal coupled to said control signal of said first sample hold circuit;
a second subtract circuit having a plus input, a minus input and an output, said plus input coupled to said output of said second sample hold circuit, said minus input coupled to said output of said amplifier;
a third sample hold circuit having an input, an output, an a control signal, said input coupled to said output of said second subtract circuit, said output coupled to said output of each respective DS circuit;
a first control signal coupled to said control inputs of first sample hold circuit and said second sample hold circuit of each respective DS circuit; and
a second control signal coupled to said control input of said third sample hold circuit of each respective DS circuit.
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9. The imaging system as in claim 4 wherein each said first DS circuit and said second DS circuit further comprises:
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a first switch having an input, a control input, and an output;
a first storage element having a first node and a second node, said first node coupled to output of said first switch;
an amplifier having an input, an output and a gain setting, said input coupled to said second node of said first storage element, said output coupled to output of each respective DS circuit;
a second storage element having a first node and a second node, said first node coupled to said second node of first storage element and said input of said amplifier;
a second switch having an input, a control input, and an output, said input coupled to said input of said amplifier, said output coupled to said output of said amplifier;
a third switch having an input, a control input, and an output, said input coupled to said output of said amplifier, said input coupled to said second node of said second storage element; and
a fourth switch having an input, a control input, and an output, said input coupled to said second node of said second storage element, said input coupled to said reference input of each respective DS circuit;
a first control signal coupled to said control input of said first switch of each respective DS circuit;
a second control signal coupled to said control inputs of said second switch and said fourth switch of each respective DS circuit; and
a third control signal coupled to said control input of said third switch of each respective DS circuit.
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10. The imaging system of claim 4 wherein the timing controller, the row decoder, the active pixel column amplifiers, and the active pixel sensor array are a single device.
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11. The imaging system of claim 4 wherein said plurality of reference pixel sensors further comprise having a shield to electromagnetic energy.
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12. The imaging system of claim 11 wherein said shield further comprises an optical mask that is opaque.
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13. The imaging system of claim 4 wherein said first common output line and said second common output line have essentially the same balanced loads.
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14. A method for sampling a set of column outputs of a pixel sensor array to create a reduced noise differential image signal, comprising the steps of:
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sampling and storing a first column output of the set of column outputs, thereby creating a first sampled value;
sampling said first column output of the set of column outputs, thereby creating a second sampled value;
subtracting said first sampled value from said second sampled value, thereby creating a first image value;
sampling and storing a voltage reference source, thereby creating a first sampled reference value;
subtracting said first image value from said first sampled reference value, thereby creating a first difference image signal;
holding a second column of the set of column outputs in a reset state;
sampling and storing said second column of the set of column outputs thereby creating a third sampled value;
sampling said second column of the set of column outputs, thereby creating a fourth sampled value;
subtracting said third sampled value from said fourth sampled value, thereby creating a second image value;
sampling and storing said voltage reference source, thereby creating a second sampled reference value; and
subtracting said second image value from said second sampled reference value, thereby creating a second difference image signal.
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15. A method for sampling an output of a pixel sensor array having a first phase, a second phase, and a third phase of operation, comprising the steps of:
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during the first phase;
sampling and storing the output of said pixel sensor array, the output having a first noise component, thereby creating a stored sampled output of said PIXEL SENSOR array;
sampling and storing a reference voltage source, which includes a second noise component, thereby creating a first stored reference voltage source;
sampling and storing said reference voltage source, which includes said second noise component, thereby creating a second stored reference voltage source;
sampling and storing a reference column output from said pixel sensor array, said reference column output held in a reset state, said reference column output having a third noise component essentially the same as said first noise component, thereby creating a stored reference column output;
during the second phase;
subtracting the output of said pixel sensor array from said stored sampled output of said pixel sensor array thereby creating a first subtracted signal;
amplifing said first subtracted signal thereby creating a first amplified subtracted signal;
subtracting said reference column output from said stored reference column output thereby creating a second subtracted signal;
amplifying said second subtracted signal thereby creating a second subtracted signal;
subtracting said first subtracted signal from said first stored reference voltage source thereby creating a third subtracted signal;
subtracting said second subtracted signal from said second stored reference voltage source thereby creating a fourth subtracted signal;
sampling and storing said third subtracted signal thereby creating a third stored subtracted signal;
sampling and storing said fourth subtracted signal thereby creating a fourth stored subtracted signal; and
during the third phase;
subtracting said fourth stored subtracted signal from said third stored subtracted signal whereby an output signal is created that essentially does not contain said first noise component, said second noise component and said third noise component.
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16. A method for sampling an output of a pixel sensor array to reduce extraneous noise components, said method having a first phase, a second phase, and a third phase, comprising the steps of:
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during the first phase;
sampling and storing said output of said pixel sensor array, said output having a first noise component;
sampling and storing a reference column output held in a reset state from said pixel sensor array, said reference column output having a second noise component, said second noise component essentially the same magnitude as said first noise component;
sampling a reference voltage source, said reference voltage source having a third noise component;
storing twice said reference voltage source with said third noise source thereby creating a first stored reference voltage source and a second stored reference voltage source;
during the second phase;
sampling and subtracting from said stored output of said pixel sensor array a reset level from said output of said pixel sensor array, said reset level having a fourth noise component, thereby creating a first resultant value;
sampling and subtracting from said stored reference column output, said reference column output held in a reset state, said reference column output having a fifth noise component, said fifth noise component essentially the same magnitude as said fourth noise component, thereby creating a second resultant value;
subtracting from said first stored reference voltage source said first resultant value thereby creating a third resultant value;
subtracting from said second stored reference voltage source said second resultant value thereby creating a fourth resultant value; and
during the third phase;
subtracting said fourth resultant value from said third resultant value thereby creating an image signal that represents said output of said pixel sensor array less said reset signal from said output of said pixel sensor array and essentially said first, second, third, fourth, and fifth noise sources are not present in said image signal.
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Specification