Apparatus for receiving and recovering frequency shift keyed symbols

• US 6,487,240 B1
• Filed: 11/10/2000
• Issued: 11/26/2002
• Est. Priority Date: 11/10/2000
• Status: Expired due to Term

• Current Assignee: North Star Innovations Inc. (Wi-LAN Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Chen, Weizhong
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Ha, Dac V.
• Application Number:
  US09/709,687
• Time in Patent Office: 746 Days
• Field of Search: 375/219, 375/269, 375/272, 375/278, 375/303, 375/334, 375/340, 375/346, 375/348, 375/350, 375/296, 708/300, 708/321, 455/42, 455/43, 455/150.1, 455/161.2, 455/188.1, 455/205, 455/214, 455/227, 455/295, 455/296, 329/300-302, 329/318
• US Class Current: 375/219
• CPC Class Codes: H04L 25/03178 Arrangements involving sequence estimation techniques
• CPC Class Codes: H04L 25/03343 Arrangements at the transmitter end
• CPC Class Codes: H04L 27/14 Demodulator circuits; Receiver circuits
• CPC Class Codes: H04L 27/2334 using filters

Abstract

A receiver architecture includes a selectivity filter (206) for selectively passing a wanted channel and rejecting unwanted channels. The selectivity filter has a filter BT of about one-half the BT of the transmitter filter. A discriminator (208) is coupled to the selectivity filter for converting received symbols from the frequency domain to the time domain symbols. A symbol recovery processor (210) is coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

Claims

1. A receiver architecture for receiving and recovering symbols transmitted over a frequency shift keyed (FSK) channel, the symbols transmitted using a transmitter filter having a ratio of transmission bandwidth to symbol rate of BT, where B is the filter half-bandwidth and T is the symbol time, the receiver architecture comprising:

a selectivity filter for selectively passing the wanted channel and rejecting unwanted channels, the selectivity filter having a filter BT of about one-half the BT of the transmitter filter;

a discriminator coupled to the selectivity filter for converting the symbols from frequency-domain symbols to time-domain symbols; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

2. The receiver architecture of claim 1, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the receiver architecture.

3. The receiver architecture of claim 1, wherein the symbol recovery processor is programmed such that the templates are optimized with a BT equal to the BT of the transmitter filter divided by approximately the square root of three.

4. The receiver architecture of claim 1, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps and a transmitter filter BT of 0.5.

5. An integrated circuit for use in a receiver for receiving and recovering symbols transmitted over a frequency shift keyed (FSK) channel, the symbols transmitted using a transmitter filter having a ratio of transmission bandwidth to symbol rate of BT, where B is the filter half-bandwidth and T is the symbol time, the integrated circuit comprising:

a selectivity filter for selectively passing the wanted channel and rejecting unwanted channels, the selectivity filter having a filter BT of about one-half the BT of the transmitter filter;

a discriminator coupled to the selectivity filter for converting the symbols from frequency-domain symbols to time-domain symbols; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

6. The integrated circuit of claim 5, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the integrated circuit.

7. The integrated circuit of claim 5, wherein the symbol recovery processor is programmed such that the templates are optimized with a BT equal to the BT of the transmitter filter divided by approximately the square root of three.

8. The integrated circuit of claim 5, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps and a transmitter filter BT of 0.5.

9. An apparatus for receiving and recovering symbols transmitted over a frequency shift keyed (FSK) channel, the symbols transmitted using a transmitter filter having a ratio of transmission bandwidth to symbol rate of BT, where B is the filter half-bandwidth and T is the symbol time, the apparatus comprising:

a selectivity filter for selectively passing the wanted channel and rejecting unwanted channels, the selectivity filter having a filter BT of about one-half the BT of the transmitter filter;

a discriminator coupled to the selectivity filter for converting the symbols from frequency-domain symbols to time-domain symbols; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

10. The apparatus of claim 9, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the apparatus.

11. The apparatus of claim 9, wherein the symbol recovery processor is programmed such that the templates are optimized with a BT equal to the BT of the transmitter filter divided by approximately the square root of three.

12. The apparatus of claim 9, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps and a transmitter filter BT of 0.5.

13. A receiver for receiving and recovering symbols transmitted over a frequency shift keyed (FSK) channel, the symbols transmitted using a transmitter filter having a ratio of transmission bandwidth to symbol rate of BT, where B is the filter half-bandwidth and T is the symbol time, the receiver comprising:

a down-converter for down-converting the wireless signal;

a selectivity filter coupled to the down-converter for selectively passing the wanted channel and rejecting unwanted channels, the selectivity filter having a filter BT of about one-half the BT of the transmitter filter;

a discriminator coupled to the selectivity filter for converting the symbols from frequency-domain symbols to time-domain symbols; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

14. The receiver of claim 13, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the receiver.

15. The receiver of claim 13, wherein the symbol recovery processor is programmed such that the templates are optimized with a BT equal to the BT of the transmitter filter divided by approximately the square root of three.

16. The receiver of claim 13, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps and a transmitter filter BT of 0.5.

17. A transceiver for receiving and recovering symbols transmitted over a frequency shift keyed (FSK) channel, the symbols transmitted using a transmitter filter having a ratio of transmission bandwidth to symbol rate of BT, where B is the filter half-bandwidth and T is the symbol time, the transceiver comprising:

a transmitter for transmitting a communication signal;

a communications processor coupled to the transmitter for controlling the transmitter; and

a receiver coupled to the communications processor for receiving the wireless signal, the receiver comprising;

a down-converter for down-converting the wireless signal;

a selectivity filter coupled to the down-converter for selectively passing the wanted channel and rejecting unwanted channels, the selectivity filter having a filter BT of about one-half the BT of the transmitter filter;

a discriminator coupled to the selectivity filter for converting the symbols from frequency-domain symbols to time-domain symbols; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

18. The transceiver of claim 17, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the transceiver.

19. The transceiver of claim 17, wherein the symbol recovery processor is programmed such that the templates are optimized with a BT equal to the transmitter filter BT divided by approximately the square root of three.

20. The transceiver of claim 17, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps and a transmitter filter BT of 0.5.

21. A wireless headset for a two-way portable communication device, the wireless headset for receiving and recovering symbols transmitted over a frequency shift keyed (FSK) channel, the symbols transmitted using a transmitter filter having a ratio of transmission bandwidth to symbol rate of BT, where B is the filter half-bandwidth and T is the symbol time, the wireless headset comprising:

a first transducer for receiving a speech input from a user;

a transmitter coupled to the first transducer for transmitting to the two-way portable communication device a communication signal comprising the speech input;

a communications processor coupled to the transmitter for controlling the transmitter;

a receiver coupled to the communications processor for receiving the wireless signal from the two-way portable communication device; and

a second transducer coupled to the receiver for conveying to the user a message received in the digital wireless signal, and

wherein the receiver comprises;

a down-converter for down-converting the wireless signal;

a selectivity filter coupled to the down-converter for selectively passing the wanted channel and rejecting unwanted channels, the selectivity filter having a filter BT of about one-half the BT of the transmitter filter;

a discriminator coupled to the selectivity filter for converting the symbols from frequency-domain symbols to time-domain symbols; and

a symbol recovery processor coupled to the discriminator for recovering the symbols through a two-state maximum likelihood sequence estimation (MLSE) technique in which templates are optimized with a BT substantially less than the BT of the transmitter filter.

22. The wireless headset of claim 21, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed such that a post-detection filter is not required in the wireless headset.

23. The wireless headset of claim 21, wherein the symbol recovery processor is programmed such that the templates are optimized with a BT equal to the BT of the transmitter filter divided by approximately the square root of three.

24. The wireless headset of claim 21, wherein the selectivity filter, the discriminator, and the symbol recovery processor are arranged and programmed to receive and recover symbols transmitted in a two-level Gaussian frequency shift keyed (2-GFSK) channel having a data rate of 1 Mbps and a transmitter filter BT of 0.5.