Multilayer wiring board, manufacturing method thereof, and wafer block contact board

• US 6,492,599 B1
• Filed: 09/12/2000
• Issued: 12/10/2002
• Est. Priority Date: 09/13/1999
• Status: Expired due to Fees

• Current Assignee: Hoya Corporation
• Original Assignee: Hoya Corporation
• Inventors: Sugihara, Osamu
• Primary Examiner(s): Talbott, David L.
• Assistant Examiner(s): PATEL, ISHWARBHAI B
• Application Number:
  US09/659,969
• Time in Patent Office: 819 Days
• Field of Search: 174/258, 174/255, 174/256, 174/259, 174/262, 174/261, 174/263, 174/264, 361/792, 361/793, 361/795, 361/812, 361/748, 361/751, 361/783, 361/746, 257/698, 257/692, 257/737, 257/778, 428/209, 428/210, 428/901
• US Class Current: 174/258
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: H05K 1/0271 Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 1/117 Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
• CPC Class Codes: H05K 2201/0154 Polyimide
• CPC Class Codes: H05K 2201/0191 wherein the thickness of the dielectric plays an important role
• CPC Class Codes: H05K 2201/0367 Metallic bump or raised conductor not used as solder bump solder materials or compositions and methods of application thereof H05K3/3457
• CPC Class Codes: H05K 2201/09481 Via in pad; Pad over filled via if used for surface mounting H05K1/113
• CPC Class Codes: H05K 2201/09672 Superposed layout, i.e. in different planes parallel traces in one plane H05K2201/09236
• CPC Class Codes: H05K 2201/10378 Interposers
• CPC Class Codes: H05K 2203/0733 Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
• CPC Class Codes: H05K 3/243 characterised by selective plating, e.g. for finish plating of pads selective plating for making the circuit pattern H05K3/108, H05K3/182
• CPC Class Codes: H05K 3/4007 Surface contacts, e.g. bumps H05K3/4092 takes precedence; deposition of finish layers on pads H05K3/24; forming solder bumps H05K3/3457
• CPC Class Codes: H05K 3/423 characterised by electroplating method
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602
• CPC Class Codes: Y10S 428/901 Printed circuit

Abstract

In a multilayer wiring board comprising: an insulating board (for example, a glass board 1); and a wiring layer (for example, wiring patterns 2a, 5a and 8a) superimposed on the insulating board through an insulating film (for example, insulating films 3 and 6), a sum (total film thickness) d (μm) of the thickness of the insulating films 3 and 6 and the internal stress f (MPa) of the insulating film satisfy the following relational expression (1):

d×<700(MPa·μm)  (1)

Claims

1. A multilayer wiring board comprising:

an insulating board; and

a wiring layer superimposed on said insulating board through an insulating film,

wherein a sum (total film thickness) d (μ

m) of the thickness of said insulating film and an internal stress f (MPa) of said insulating film satisfy the following relational expression (1);

2. The multilayer wiring board according to claim 1, wherein said sum (total film thickness) d of the thickness of said insulating film is not less than 0.1 μ

m and less than 50 μ

m, and said internal stress f of said insulating film is not less than 14 MPa and less than 7000 MPa.

3. The multilayer wiring board according to claim 1, wherein the coefficient of thermal expansion of said insulating board is not more than 10 ppm/°

C.

4. A multilayer wiring board according to claim 1, wherein a corner portion of a wiring in said wiring layer has an angle of not less than 120°

so that at most a crack is barely generated in said insulating film.

5. A multilayer wiring board according to claim 1, wherein an edge and/or a corner portion of a wiring in said wiring layer is formed so as to be shifted from an edge and/or a corner portion of a wiring in another wiring layer superimposed through said insulating film by not less than 100 μ

m in a plane direction.

6. A multilayer wiring board according to claim 1, wherein a protective film is formed only at a contact terminal portion in an uppermost wiring layer.

7. A multilayer wiring board according to claim 1, wherein the thickness of a protective film for the contact terminal portion in an uppermost wiring layer of said multilayer wiring board falls within a range of 300 angstrom to 30 μ

m.

8. A multilayer wiring board according to claim 1, wherein an uppermost layer of a protective film for a contact terminal portion in an uppermost wiring layer of said multilayer wiring board is a thin film which consists of a noble metal or mainly consists of a noble metal having the thickness of not more than 0.8 μ

m.

9. A multilayer wiring board according to claim 1, wherein a protective film for a contact terminal portion in an uppermost wiring layer of said multilayer wiring board is an Ni/Au thin film sequentially formed on said uppermost wiring layer.

10. A multilayer wiring board for a wafer block contact board according to claim 1, wherein said multilayer wiring board is a multilayer wiring board constituting a part of a wafer block contact board used for carrying out a test of a plurality of semiconductor devices formed on a wafer in a lump.

11. A multilayer wiring board according to claim 1, wherein a corner portion of a wiring in said wiring layer has a rounded shape so that at most a crack is barely generated in said insulating film.

12. A multilayer wiring board according to claim 1, wherein a contact terminal portion in an uppermost layer of said multilayer wiring board has a width of not more than 10 mm, preventing said contact terminal portion from being peeled.

13. The multilayer wiring board of claim 12, wherein said contact terminal portion is segmented by a hole to be meshed.

14. The multilayer wiring board of claim 12, wherein said contact terminal portion has a corner portion which is rounded.

15. The multilayer wiring board of claim 12, wherein said contact terminal portion is segmented by a hole to be meshed and has a corner portion which is rounded.