Memory device which receives write masking and automatic precharge information

• US 6,493,789 B2
• Filed: 09/28/2001
• Issued: 12/10/2002
• Est. Priority Date: 10/19/1995
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Griffin, Matthew Murdy, Stark, Donald Charles, Hampel, Craig Edward, Ware, Frederick Abbott
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/966,126
• Publication Number:
  US 20020010832A1
• Time in Patent Office: 438 Days
• Field of Search: 711/105, 711/167, 711/168, 365/189.04, 365/233
• US Class Current: 711/105
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor memory device which includes a set of interface terminals to receive a plurality of control signals which specify that the memory device receive a first set of data bits and a second set of data bits. The plurality of control signals further specify that the memory device precharge sense amplifiers used in writing the first set of data bits to an array of memory cells, and precharge sense amplifiers used in writing the second set of data bits to the array of memory cells. The memory device further includes a mask terminal to receive a first mask bit during a first half of a clock cycle of an external clock signal, the first mask bit to indicate whether to write the first set of data bits to the array. The mask terminal further receives a second mask bit during a second half of the clock cycle of the external clock signal, the second mask bit to indicate whether to write the second set of data bits to the array.

Claims

1. A method of operation in a semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, wherein the method comprises:

receiving a plurality of control signals which specify that the memory device perform a memory write operation and a precharge operation, wherein the precharge operation is performed automatically following the memory write operation;

receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit, wherein the first mask bit indicates whether to write the first data value to the array;

receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit, wherein the second mask bit indicates whether to write the second data value to the array;

when the first mask bit indicates that the first data value is to be written to the array, writing the first data value to the array during the memory write operation;

when the second mask bit indicates that the second data is to be written to the array, writing the second data value to the array during the memory write operation; and

during the precharge operation, precharging a plurality of sense amplifiers that are used in writing the first and second data values to the array.

2. The method of claim 1 wherein a first control value is encoded in the plurality of control signals to specify that the precharge operation is performed automatically following the memory write operation.

3. The method of claim 1 further including:

receiving a plurality of control signals which specify that the memory device perform a row sensing operation; and

activating a row of memory cells during the row sensing operation.

4. The method of claim 3 wherein:

if the first mask bit indicates that the first data value is to be written, then the first data value is written to a first memory location in the row of memory cells; and

if the second mask bit indicates that the second data value is to be written, then the second data value is written to a second memory location in the row of memory cells.

5. The method of claim 4 wherein the first memory location is identified by a column address.

6. The method of claim 1 wherein the memory device is a dynamic random access memory device.

7. The method of claim 1 wherein the memory device includes a pin to receive the first and second mask bits, the method further including receiving error detection and correction information on the pin.

8. A semiconductor memory device which includes sense amplifiers coupled to an array of memory cells, wherein the memory device comprises:

a set of interface terminals to receive a plurality of control signals which specify that the memory device;

receive a first set of data bits and a second set of data bits;

precharge sense amplifiers used in writing the first set of data bits to the array; and

precharge sense amplifiers used in writing the second set of data bits to the array; and

a mask terminal to receive;

a first mask bit during a first half of a clock cycle of an external clock signal, the first mask bit to indicate whether to write the first set of data bits to the array; and

a second mask bit during a second half of the clock cycle of the external clock signal, the second mask bit to indicate whether to write the second set of data bits to the array.

9. The memory device of claim 8 wherein the memory cells are dynamic random access memory cells.

10. The memory device of claim 8 wherein the memory device receives error detection and correction information on the mask terminal.

11. The memory device of claim 8 wherein:

the first set of data bits is received during a half of a clock cycle which is temporally offset from the first half of the clock cycle of the external clock signal by a number of clock cycles of the external clock signal; and

the second set of data bits is received during a half of a clock cycle which is temporally offset from the second half of the clock cycle of the external clock by the number of clock cycles of the external clock signal.

12. The memory device of claim 8 further including a plurality of pins to receive the first set of data bits and the second set of data bits from a set of external signal lines.

13. The memory device of claim 8 wherein:

the first set of data bits is received during the first half of the clock cycle of the external clock signal; and

the second set of data bits is received during the second half of the clock cycle of the external clock signal.

14. The memory device of claim 8 further including a plurality of pins, coupled to the set of interface terminals, to receive the plurality of control signals.

15. The memory device of claim 8 wherein both the first set of data bits and the second set of data bits are received on the set of interface terminals.

16. The memory device of claim 15 wherein the plurality of control signals are received during a first clock cycle of the external clock signal, and the first and second sets of data bits are received during a second clock cycle of the external clock signal.

17. The memory device of claim 16 wherein the plurality of control signals are included in a request packet.

18. The memory device of claim 8 wherein the mask terminal also receives a data bit, wherein the first mask bit, the second mask bit and the data bit are received by the mask terminal in a multiplexed format.

19. A method of controlling a synchronous semiconductor memory device, wherein the memory device includes a plurality of sense amplifiers coupled to an array of memory cells, wherein the method comprises:

providing a first control value to the memory device, wherein the first control value indicates that the memory device;

receive a first set of data bits and a second set of data bits;

precharge sense amplifiers used in writing the first set of data bits to the array; and

precharge sense amplifiers used in writing the second set of data bits to the array;

providing to the memory device, during a first half of a clock cycle of an external clock signal, the first set of data bits and a first mask bit, wherein the first mask bit indicates whether to write the first set of data bits to the array; and

providing to the memory device, during a second half of the clock cycle of the external clock signal, the second set of data bits and a second mask bit, wherein the second mask bit indicates whether to write the second set of data bits to the array.

20. The method of claim 19 wherein:

if the first set of data bits is written to the array, the sense amplifiers used in writing the first set of data bits to the array is precharged after the first set of data bits is written to the array; and

if the second set of data bits is written to the array, the sense amplifiers used in writing the second set data bits to the array is precharged after the second set of data bits is written to the array.

21. The method of claim 19 wherein:

the first set of data bits are provided in parallel during the first half of the clock cycle of the external clock signal; and

the second set of data bits are provided in parallel during the second half of the clock cycle of the external clock signal.

24. The method of claim 19 wherein the first and second mask bits are provided over an external signal line.

25. The method of claim 24 wherein the first and second mask bits are provided over the same external signal line.

26. The method of claim 19 further including providing a second control value to the memory device, wherein the second control value indicates that the memory device initiate a row sensing operation, wherein the memory device transfers data stored in a row of the array of memory cells to a row of sense amplifiers during the row sensing operation.

27. The method of claim 26 wherein the first set of data bits and the second set of data bits are provided to the memory device during a column access operation, wherein, during the column access operation:

if the first mask bit indicates that the first set of data bits is to be written, then the first set of data bits is written to a specific column location in the row of the array of memory cells; and

if the second mask bit indicates that the second set of data bits is to be written, then the second set of data bits is written to the specific column location in the row of the array of memory cells.

22. The method of claim further 19 including providing, to the memory device, information that instructs the memory device to ignore the first and second mask bits.

23. The method of claim 22 wherein the information is stored in a register on the memory device in response to a control signal, the method further including providing the control signal to the memory device.

28. A semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, wherein the memory device comprises:

a plurality of pins to receive a control value which specifies that the memory device perform a write operation and a precharge operation, wherein the precharge operation is performed automatically following the write operation;

an input pin to receive;

a first mask bit during a first half of a clock cycle of the external clock signal, wherein the first mask bit indicates whether to write a first data value to the array during the memory write operation; and

a second mask bit during a second half of the clock cycle of the external clock signal, wherein the second mask bit indicates whether to write a second data value to the array during the memory write operation; and

a plurality of sense amplifiers coupled to the memory array to write, during the memory write operation, the first data value to the array in accordance with the first mask bit and the second data value to the array in accordance with the second mask bit, wherein the plurality of sense amplifiers is precharged during the precharge operation.

29. The memory device of claim 28 further including control logic circuitry, coupled to the plurality of pins, to decode the control value.

30. The memory device of claim 28 further including a plurality of pins to receive the first data value and the second data value.

31. The memory device of claim 28 wherein:

the first data value is received during the first half of the clock cycle of the external clock signal; and

the second data value is received during the second half of the clock cycle of the external clock cycle.

32. The memory device of claim 28 wherein the memory cells include dynamic random access memory cells.

33. The memory device of claim 28 wherein the input pin further receives a bit of data, and wherein the first mask bit, the second mask bit and the bit of data are received from the input pin in a multiplexed format.

34. The memory device of claim 28 wherein:

the first data value is received during a clock cycle which is temporally offset from the first half of the clock cycle of the external clock signal by a number of clock cycles of the external clock signal; and

the second data value is received during the clock cycle which is temporally offset from the second half of the clock cycle of the external clock by the number of clock cycles of the external clock signal.

35. The memory device of claim 34 wherein the control value is included in a request packet.

36. The memory device of claim 28 wherein:

the control value is received during a first transition of the external clock signal; and

both the first set of data bits and the second set of data bits are received during a second transition of the external clock signal.