Transfer controller with hub and ports architecture

• US 6,496,740 B1
• Filed: 04/06/2000
• Issued: 12/17/2002
• Est. Priority Date: 04/21/1999
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Hoyle, David, Robertson, Iain
• Primary Examiner(s): PATEL, RAMESH B
• Application Number:
  US09/543,870
• Time in Patent Office: 985 Days
• Field of Search: 700/2-5, 700/7, 700/26, 700/25, 700/19-20, 700/11-12, 710/2, 710/22, 710/23, 710/26, 710/28, 710/33, 710/107, 710/119, 710/14, 710/48, 710/308, 710/54, 712/36, 712/35, 712/34, 712/38
• US Class Current: 700/20
• CPC Class Codes: G06F 15/17 using an input/output type connection, e.g. channel, I/O port

Abstract

The transfer controller with hub and ports (TCHP) performs the task of communication throughout an entire system in a centralized function. A single hub (435) tied to multiple ports (440, 447, 450, 452) by a central pipeline is the medium for all data communications among DSP clusters (455), external devices, and external memory. A transfer request queue manager (420) receives, prioritizes and queues data transfer requests. Each data port includes an identically configured interior interface (901) connected to the hub (435) and an exterior interface (902) configured for a target external memory/device connected to the port. The interior interfaces of all ports are clocked at a common internal frequency, while the exterior interfaces are clocked at the frequency of the external memory/device connected to the port.

Claims

1. A data transfer controller comprising.

a request queue controller capable of receiving, prioritizing and dispatching data transfer requests each specifying a data source, a data destination and a data quantity to be transferred;

a data transfer hub connected to the request queue controller for receiving dispatched data transfer requests;

a plurality of ports, each port having an interior interface connected to the data transfer hub which is the same for each port and an exterior interface configured for an external memory/device which, in operation, is connected to said port, the interior interface and the exterior interface being connected for data transfer therebetween; and

the data transfer hub being capable of controlling data transfers from a source port corresponding to the data source to a destination port corresponding to the data destination in quantities corresponding to the data quantities to be transferred under a currently executing data transfer request.

2. The data transfer controller of claim 1, wherein:

said data transfer hub and said interior interface of each of said plurality ports are clocked at first common frequency;

said exterior interface of each of said plurality of ports is clocked at a second frequency corresponding to external memory/device expected to be connected to said port, said second frequency of at least one of said plurality of ports being asynchronous with said first common frequency.

3. The data transfer controller of claim 1, wherein:

said data transfer hub includes a plurality of data channels, each data channel having a source address calculation unit, a destination address calculation unit and a data first-in-first-out buffer, said data transfer hub controlling

reading of data by supply of a source address calculated by said source address calculation unit to said source port and supplying data read from said source port to an input of said data first-in-first-out buffer, and

writing of data by supply of a destination address calculated by said destination address calculation unit to said destination port and supplying data to be written to said destination port from an output of said data first-in-first-out buffer.

4. The data transfer controller of claim 3, wherein:

said data transfer request specifies a data source by specifying a source base address, a source interval and a source word count; and

said source address calculation unit includes

a source base address register initially loaded with said source base address,

a source interval address register initially loaded with said source interval,

a source word count register initially loaded with said source word count,

a source address adder connected to said source base address register and said source interval address register, said source address adder calculating a next source address by adding data stored in said source base address register to data stored in said source interval address register and storing said next source address in said source base address register, and

a source word count decrementer connected to said source word count register decrementing said word count stored in said source word count register for each calculated next source address, said data transfer hub ending data transfer in response to a data transfer request when said source word count stored in said source word count register has decremented to zero.

5. The data transfer controller of claim 3, wherein:

said data transfer request specifies a data destination by specifying a destination base address, a destination interval and a destination word count; and

said destination address calculation unit includes

a destination base address register initially loaded with said destination base address,

a destination interval address register initially loaded with said destination interval,

a destination word count register initially loaded with said destination word count,

a destination address adder connected to said destination base address register and said destination interval address register, said destination address adder calculating a next destination address by adding data stored in said destination base address register to data stored in said destination interval address register and storing said next destination address in said destination base address register, and

a destination word count decrementer connected to said destination word count register decrementing said word count stored in said destination word count register for each calculated next destination address, said data transfer hub ending data transfer in response to a data transfer request when said destination word count stored in said destination word count register has decremented to zero.

6. The data transfer controller of claim 1, wherein:

said data transfer hub includes a plurality of data channels, each data channel having a source address calculation unit, a destination address calculation unit and a data first-in-first-out buffer, said data transfer hub controlling

reading of data by supply of a source address calculated by said source address calculation unit to said source port and supplying data read from said source port to an input of said data first-in-first-out buffer,

writing of data by supply of a destination address calculated by said destination address calculation unit to said destination port and supplying data to be written to said destination port from an output of said data first-in-first-out buffer until said data quantity specified in said data transfer request has been transferred, whereupon said data channel is open;

said data transfer requests each have a priority within a hierarchy of priorities;

said request queue controller dispatching data transfer requests to an open data channel of said data transfer hub in priority order from highest to lowest priority within said hierarchy of priorities and within each priority level from a first received data request to a last received data transfer request.

7. The data transfer controller of claim 6, wherein:

said data transfer hub controlling a data transfer request until said data transfer request completes or generates a fault once assigned to a data channel.

8. The data transfer controller of claim 6, wherein:

said request queue controller includes a request queue memory storing data transfer requests upon receipt prior to dispatch, said request queue memory having a data capacity to store more data transfer requests than a number of data channels of said data transfer hub.

9. A data processing system comprising:

a plurality of data processors, each data processor being capable of generating a data transfer request;

a request queue controller connected to the plurality of data processors for receiving, prioritizing and dispatching data transfer requests each specifying a data source, a data destination and a data quantity to be transferred;

a data transfer hub connected to the request queue controller for receiving dispatched data transfer requests;

a plurality of ports, each port having an interior interface connected to said data transfer hub which is the same for each port and an exterior interface configured for an external memory/device which in operation is connected to the port, the interior interface and said exterior interface being connected for data transfer therebetween; and

the data transfer hub being capable of controlling data transfers from a source port corresponding to the data source to a destination port corresponding to the data destination in quantities corresponding to the data quantities to be transferred under a currently executing data transfer request.

10. The data processing system of claim 9, wherein:

each of said data processors, said data transfer hub and said interior interface of each of said plurality ports are clocked at first common frequency;

said exterior interface of each of said plurality of ports is clocked at a second frequency corresponding to external memory/device expected to be connected to said port, said second frequency of at least one of said plurality of ports being asynchronous with said first common frequency.

11. The data processing system of claim 9, further comprising:

a system memory connected to a predetermined one of said plurality of ports; and

wherein each of said data processors includes a program cache for temporarily storing program instructions controlling said data processor, said data processor generating a data transfer for program cache fill from said system memory upon a read access miss to said program cache.

12. The data processing system of claim 9, further comprising:

a system memory connected to a predetermined one of said plurality of ports; and

wherein each of said data processors includes a data cache for temporarily storing data employed by said data processor, said data processor generating a data transfer for data cache fill from said system memory upon a read access miss to said data cache.

13. The data processing system of claim 9, further comprising:

a system memory connected to a predetermined one of said plurality of ports; and

wherein each of said data processors includes a data cache for temporarily storing program instructions, said data processor generating a data transfer for data writeback to said system memory upon a write miss to said data cache.