Semiconductor memory device which receives write masking information
DCFirst Claim
1. A method of operation in a semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, the method comprises:
- receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit, wherein the first mask bit indicates whether to write the first data value to the array; and
receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit, wherein the second mask bit indicates whether to write the second data value to the array.
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Abstract
A semiconductor memory device and a method of operation in the semiconductor memory device. The memory device receives an external clock signal and includes an array of memory cells. The method of operation of the memory device includes receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit. The first mask bit indicates whether to write the first data value to the array. The method further includes receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit. The second mask bit indicates whether to write the second data value to the array.
211 Citations
39 Claims
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1. A method of operation in a semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, the method comprises:
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receiving, during a first half of a clock cycle of the external clock signal, a first data value and a first mask bit, wherein the first mask bit indicates whether to write the first data value to the array; and
receiving, during a second half of the clock cycle of the external clock signal, a second data value and a second mask bit, wherein the second mask bit indicates whether to write the second data value to the array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
initiating a write operation; and
precharging a portion of the array of memory cells after initiating the write operation.
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9. The method of claim 1 further including receiving information that instructs the memory device to ignore the first and second mask bits.
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10. The method of claim 9 further including storing the information in a register on the memory device.
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11. The method of claim 10 wherein the information stored in the register is altered in response to a control signal.
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12. The method of claim 1 wherein the first and second mask bits are received from an external signal line.
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13. The method of claim 12 wherein the first and second mask bits are received from the same external signal line.
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14. The method of claim 12 further including receiving a data bit from the external signal line, wherein the first mask bit, second mask bit and the data bit are multiplexed over the external signal line.
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15. A synchronous semiconductor memory device, wherein the memory device receives an external clock signal and includes an array of memory cells, the memory device comprises:
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a pin to receive a first mask bit during a first half of a clock cycle of the external clock signal and to receive a second mask bit during a second half of the clock cycle of the external clock signal; and
an interface to receive;
a first data value with the first mask bit, wherein the first mask bit indicates whether to write the first data value to the array; and
a second data value with the second mask bit, wherein the second mask bit indicates whether to write the second data value to the array. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26)
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27. A method of controlling a synchronous semiconductor memory device by a memory controller, wherein the memory device includes an array of memory cells, the method comprises:
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providing to the memory device, during a first half of a clock cycle of an external clock signal, a first set of data bits and a first mask bit, wherein the first mask bit indicates whether to write the first set of data bits to the array; and
providing to the memory device, during a second half of the clock cycle of the external clock signal, a second set of data bits and a second mask bit, wherein the second mask bit indicates whether to write the second set of data bits to the array. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39)
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Specification