SOI semiconductor integrated circuit for eliminating floating body effects in SOI MOSFETs and method of fabricating the same

• US 6,498,370 B1
• Filed: 10/24/2000
• Issued: 12/24/2002
• Est. Priority Date: 10/25/1999
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Hee-Sung, Park, Sung-Bae, Kim, Byung-Sun, Kim, Young-Wug, Ko, Young-Gun
• Primary Examiner(s): Elms, Richard
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/695,341
• Time in Patent Office: 791 Days
• Field of Search: 257/347, 438/149
• US Class Current: 257/347
• CPC Class Codes: H01L 29/78615 with a body contact

Abstract

A silicon-on-insulator (SOD integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Claims

1. A silicon-on-insulator (SOI) semiconductor integrated circuit formed on an SOI substrate including a supporting substrate, a buried insulating layer on the supporting substrate and a semiconductor layer of a first conductivity type on the buried insulating layer, the integrated circuit comprising:

at least one isolated transistor active region comprising a predetermined region of the semiconductor layer;

a body line of the first conductivity type disposed at one side of the transistor active region, the body line including a portion of the semiconductor layer;

an isolation layer surrounding sidewalls of the transistor active region and the body line, the isolation layer being in contact with the buried insulating layer;

a body extension of the first conductivity type extended from a predetermined sidewall of the transistor active region and connected to the body line, the body extension being thinner than the transistor active region;

a body insulating layer formed on the body extension; and

an insulated gate pattern crossing over the transistor active region, the insulated gate pattern overlapping with the body insulating layer.

2. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the first conductivity type is one of P-type and N-type.

3. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising a metal silicide layer formed on the body line.

4. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising a gate insulating layer interposed between the insulated gate pattern and the transistor active region.

5. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising an insulating spacer formed on a sidewall of the insulated gate pattern.

6. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the gate pattern comprises a conductive gate electrode.

7. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 6, further comprising a metal silicide layer formed on the gate electrode.

8. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the gate pattern comprises a conductive gate electrode and a capping insulating layer formed on the gate electrode.

9. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising:

a source region formed at the transistor active region and located at one side of the gate pattern; and

a drain region formed at the transistor active region and located at the other side of the gate pattern, the source and drain regions having a second conductivity type opposite to the first conductivity type.

10. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 9, further comprising a metal silicide layer formed on the source and drain regions.

11. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, further comprising one of a ground line and a power line running over the body line, the one of the ground line and the power line being electrically connected to the body line.

12. The silicon-on-insulator (SOI) semiconductor integrated circuit of claim 1, wherein the body line is a straight line.

13. The silicon-on-insulator (SOD semiconductor integrated circuit of claim 1, wherein the at least one transistor active region comprises a plurality of transistor active regions.

14. The silicon-on-insulator (SOD semiconductor integrated circuit of claim 13, wherein the plurality of transistor active regions are disposed at one side or both sides of the body line.