Semiconductor device

• US 6,501,129 B2
• Filed: 03/29/2001
• Issued: 12/31/2002
• Est. Priority Date: 03/30/2000
• Status: Expired due to Term

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Osawa, Akihiko
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Huynh, Andy
• Application Number:
  US09/820,369
• Publication Number:
  US 20010025984A1
• Time in Patent Office: 642 Days
• Field of Search: 257/339, 257/327, 257/328, 257/329, 257/330, 257/331, 257/332, 257/334, 257/133, 257/302, 257/270, 257/500, 257/502, 257/493, 257/471
• US Class Current: 257/330
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Formed in a part of the base region is an impurity diffusion region extending in a vertical direction and having an impurity concentration lower than that in the other portion of the base region. By the formation of the impurity diffusion region, the depletion layer is extended toward the base region so as to improve the breakdown voltage. The impurity diffusion region is formed by forming a trench in a part of the base region, a conductive film being buried in the trench, followed by introducing by ion implantation an impurity of the conductivity type equal to that in the base region into the side wall and the bottom of the trench in a concentration lower than that in the base region and subsequently diffusing the implanted impurity ions. The impurity diffusion region thus formed permits relaxing the electric field concentration on the corner portion of the gate trench and on the extended portion of the base region so as to improve the breakdown voltage.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate;

a semiconductor layer of a first conductivity type formed on one main surface region of said semiconductor substrate;

a drain region of the first conductivity type formed in said semiconductor layer of the first conductivity type;

a base region of a second conductivity type formed in a surface region of said drain region;

a source region of the first conductivity type formed in a surface region of said base region;

a trench having at least one of a conductive layer and an insulating layer buried therein and extending from the surface of the base region through the base region to reach an inner region of the drain region;

an impurity diffusion region of the second conductivity type formed in the periphery of the side wall of that portion of the trench which is positioned within the drain region and having an impurity concentration lower than that in the base region;

a gate insulating film formed to cover a part of the surfaces of the drain region, the base region and the source region; and

a gate electrode formed on the gate insulating film.

2. The semiconductor device according to claim 1, wherein the semiconductor substrate is of the first conductivity type.

3. The semiconductor device according to claim 1, wherein the semiconductor substrate is of the second conductivity type.

4. A semiconductor device, comprising:

a semiconductor substrate;

a semiconductor layer of a first conductivity type formed on one main surface region of said semiconductor substrate;

a drain region of the first conductivity type formed in said semiconductor layer of the first conductivity type;

a base region of a second conductivity type formed in a surface region of said drain region;

a source region of the first conductivity type formed in a surface region of said base region;

a first trench having at least one of a conductive layer and an insulating layer buried therein and extending from the surface of the base region through the base region to reach an inner region of the drain region;

an impurity diffusion region of the second conductivity type formed in the periphery of the side wall of that portion of the first trench which is positioned within the drain region and having an impurity concentration lower than that in the base region;

a second trench extending from the surface of the source region or from the surface of that portion of the base region which is contiguous to the source region to reach an inner region of the drain region;

a gate insulating film formed in the side wall and the bottom region of said second trench; and

a gate electrode buried in said second trench in a manner to cover said gate insulating film.

5. The semiconductor device according to claim 4, wherein the semiconductor substrate is of the first conductivity type.

6. The semiconductor device according to claim 4, wherein the semiconductor substrate is of the second conductivity type.

7. The semiconductor device according to claim 4, wherein the depth of the first trench from the surface of the base region is larger than that of the second trench from the surface of the source region or from the surface of that portion of the base region which is contiguous to the source region.

8. The semiconductor device according to claim 7, wherein the semiconductor substrate is of the first conductivity type.

9. The semiconductor device according to claim 7, wherein the semiconductor substrate is of the second conductivity type.

10. The semiconductor device according to claim 9, wherein a buffer layer formed of a semiconductor layer of the first conductivity type having an impurity concentration higher than that in the semiconductor layer of the first conductivity type is formed between the semiconductor substrate and the semiconductor layer of the first conductivity type.