Method and apparatus for enhanced SOI passgate operations

• US 6,504,212 B1
• Filed: 02/03/2000
• Issued: 01/07/2003
• Est. Priority Date: 02/03/2000
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Allen, David Howard, Kuang, Jente Benedict, Lu, Pong-Fei, Stasiak, Daniel Lawrence, Saccamango, Mary Joseph
• Primary Examiner(s): Lee, Eddie
• Assistant Examiner(s): Warren, Matthew E.
• Application Number:
  US09/497,361
• Time in Patent Office: 1,069 Days
• Field of Search: 257/347, 257/348, 257/351, 257/355, 257/356, 257/547
• US Class Current: 257/347
• CPC Class Codes: G11C 2207/002 Isolation gates, i.e. gates coupling bit lines to the sense amplifier
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: H01L 29/7841 with floating body, e.g. programmable transistors
• CPC Class Codes: H01L 29/78615 with a body contact
• CPC Class Codes: H03K 17/063 in field-effect transistor switches
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit

Abstract

A method and apparatus are provided for implementing enhanced silicon-on-insulator (SOI) passgate operations. The apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations includes a silicon-on-insulator (SOI) passgate field effect transistor. A select input is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. A discharging field effect transistor of an opposite channel type is coupled to the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is activated during an off cycle of the silicon-on-insulator (SOI) passgate field effect transistor. The discharging field effect transistor is coupled to the body of the SOI passgate field effect transistor. The discharging field effect transistor is deactivated during an on cycle of the SOI passgate field effect transistor, whereby the body of the SOI passgate field effect transistor floats during the on cycle. The method for implementing enhanced silicon-on-insulator (SOI) passgate operations can be used with N-channel or P-channel implementations as well as with a combination of N-channel and P-channel devices.

Claims

1. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations comprising:

a silicon-on-insulator (SOI) passgate field effect transistor;

a select input coupled to said silicon-on-insulator (SOI) passgate field effect transistor; and

a discharging field effect transistor of an opposite channel type coupled to said silicon-on-insulator (SOI) passgate field effect transistor;

said discharging field effect transistor being activated only during an off cycle of said silicon-on-insulator (SOI) passgate field effect transistor.

2. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 1 wherein said discharging field effect transistor is coupled to a body of said silicon-on-insulator (SOI) passgate field effect transistor.

3. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 2 wherein said discharging field effect transistor is deactivated during an on cycle of said silicon-on-insulator (SOI) passgate field effect transistor, whereby said body of said silicon-on-insulator (SOI) passgate field effect transistor floats during said on cycle.

4. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 1 wherein said silicon-on-insulator (SOI) passgate field effect transistor is a SOI N-channel field effect transistor (NFET).

5. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 4 wherein said select input coupled to a gate input of said silicon-on-insulator (SOI) passgate NFET.

6. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 5 wherein said discharging field effect transistor is a silicon-on-insulator (SOI) P-channel field effect transistor (PFET).

7. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 6 wherein said select input coupled to a gate input of said discharging silicon-on-insulator (SOI) PFET.

8. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 7 wherein said discharging silicon-on insulator (SOI) PFET has a source connected to a body of said silicon-on-insulator (SOI) passgate NFET and has a drain connected to ground.

9. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 1 wherein said silicon-on-insulator (SOI) passgate field effect transistor is a SOI P-channel field effect transistor (PFET).

10. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 9 wherein said select input is an inverted select input coupled to a gate input of said silicon-on-insulator (SOI) passgate PFET.

11. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 10 wherein said discharging field effect transistor is a silicon-on-insulator (SOI) N-channel field effect transistor (NFET).

12. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 11 wherein said inverted select input coupled to a gate input of said discharging silicon-on-insulator (SOI) NFET.

13. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 12 wherein said discharging silicon-on insulator (SOI) NFET has a source connected to a supply voltage and has a drain connected to body of said silicon-on-insulator (SOI) passgate PFET.

14. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 12 wherein said silicon-on-insulator (SOI) passgate transistor includes a SOI N-channel field effect transistor (NFET) and a SOI P-channel field effect transistor (PFET).

15. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations as recited in claim 14 wherein said discharging field effect transistor includes a PFET connected between a body of said silicon-on-insulator (SOI) passgate NFET and ground;

and an NFET connected between a supply voltage and a body of said silicon-on-insulator (SOI) passgate PFET.

16. Apparatus for implementing enhanced silicon-on-insulator (SOI) passgate operations comprising:

a silicon-on-insulator (SOI) passgate N-channel field effect transistor (NFET);

a select input coupled to a gate of said silicon-on-insulator (SOI) passgate NFET; and

a discharging P-channel field effect transistor (PFET) coupled to a body of said silicon-on-insulator (SOI) passgate NFET;

said select input coupled to a gate of said discharging PFET for activating said discharging PFET during an off cycle of said silicon-on-insulator (SOI) passgate NFET.