Redundant bit steering mechanism with delayed switchover of fetch operations during redundant device initialization

• US 6,505,306 B1
• Filed: 09/15/1999
• Issued: 01/07/2003
• Est. Priority Date: 09/15/1999
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Haselhorst, Kent Harold, Marcella, James Anthony, Drehmel, Robert Allen, Blackmon, Herman Lee
• Primary Examiner(s): Beausoleil, Robert
• Assistant Examiner(s): WILSON, YOLANDA L
• Application Number:
  US09/396,973
• Time in Patent Office: 1,210 Days
• Field of Search: 714/6, 714/42, 714/13, 714/7, 714/710, 714/723, 714/764, 714/767
• US Class Current: 714/6.1
• CPC Class Codes: G11C 29/76 using address translation or modifications

Abstract

An apparatus, program product and method initialize a redundant memory device by delaying the switchover of non-initialization fetch operations from a failed memory device to the redundant memory device until after initialization of the redundant memory device is complete. Consequently, during initialization, the non-initialization fetch operations are directed to the failed memory device, while non-initialization store operations are directed to the redundant device.

Claims

1. An apparatus, comprising:

(a) a memory array including a plurality of memory devices; and

(b) a memory controller coupled to the memory array, the memory controller configured to initialize a redundant memory device from the plurality of memory devices with data stored in a failed memory device from the plurality of memory devices by directing any non-initialization fetch operations associated with the failed memory device to the failed memory device, directing any non-initialization store operations associated with the failed memory device to the redundant memory device, and processing an initialization operation by copying data from the failed memory device to the redundant memory device.

2. The apparatus of claim 1, wherein the plurality of memory devices include a plurality of primary memory devices that include the failed memory device, each primary memory device including at least one data line configured to supply a primary data bit, wherein the redundant memory device includes at least one data line configured to supply a redundant data bit.

8. The apparatus of claim 1, wherein the memory controller is configured to direct any non-initialization fetch operations associated with the failed memory device to the failed memory device, and direct any non-initialization store operations associated with the failed memory device to the redundant memory device, during processing of the initialization operation.

3. An apparatus, comprising:

(a) a memory array including a plurality of memory devices; and

(b) a memory controller coupled to the memory array, the memory controller configured to initialize a redundant memory device from the plurality of memory devices with data stored in a failed memory device from the plurality of memory devices by directing any non-initialization fetch operations associated with the failed memory device to the failed memory device non-initialization store operations associated with the failed memory device to the redundant memory device, and processing an initialization operation by copying data from the failed memory device to the redundant memory device, wherein the plurality of memory devices include a plurality of primary memory devices that include the failed memory device, each primary memory device including at least one data line configured to supply a primary data bit, wherein the redundant data bit, and wherein the memory controller includes;

(i) a plurality of fetch multiplexers, each fetch multiplexer including first and second data inputs, a select input and an output, the first input coupled to receive the primary data bit from an associated primary memory device, the second input coupled to receive the redundant data bit from the redundant memory device, and the output configured to output either the primary data bit from the associated primary memory device or the redundant data bit responsive to a select signal provided to the select input;

(ii) a store multiplexer including a plurality of data inputs, a select input and an output, the output coupled to the data line from the redundant memory device, and the plurality of data inputs configured to receive a plurality of primary data bits forming a data word to be stored in the memory array; and

(iii) selection logic coupled to the select inputs of the fetch and store multiplexers, the selection logic responsive to redundant bit steering information to drive the select input of the store multiplexer to control the store multiplexer to output the primary data bit associated with the failed memory device to the redundant memory device.

4. The apparatus of claim 3, wherein the selection logic is further responsive to an initialization indicator that indicates whether the redundant memory device is being initialized, wherein, when the initialization indicator indicates that the redundant memory device is being initialized, the selection logic is configured to drive the select input of each of the fetch multiplexers to control each fetch multiplexer to output the primary data bit from the associated primary memory device, and when the initialization indicator indicates that the redundant memory device is not being initialized, the selection logic is responsive to the redundant bit steering information to drive the select input of the fetch multiplexer associated with the failed memory device to control such fetch multiplexer to output the redundant data bit in lieu of the primary data bit associated with the failed memory device.

5. The apparatus of claim 4, wherein the memory controller further includes a redundant bit steering array including a plurality of entries, each entry associated with one of a plurality of extents defined in the memory array, and each entry storing an initialization indicator and redundant bit steering information for the associated extent.

6. The apparatus of claim 4, wherein the memory controller further includes:

(a) error correction logic coupled to the outputs of the fetch multiplexers, the error correction logic configured to generate a corrected fetch data word from the data bits output from the fetch multiplexers; and

(b) error recovery code generation logic configured to receive a store data word and generate therefrom an error recovery code, the error recovery code generation logic configured to output the store data word and the error recovery code to both the memory array and the store multiplexer.

7. The apparatus of claim 6, wherein the memory controller further includes initialization logic coupled to the selection logic and the memory array, the initialization logic configured to, responsive to detection of a failure in a primary memory device, generate redundant bit steering information identifying the failed memory device, assert the initialization indicator, initiate a plurality of fetch and store operations associated with the failed memory device to copy data from the failed memory device to the redundant memory device, and thereafter deassert the initialization indicator.

9. A circuit arrangement for use in controlling a memory array including a plurality of memory devices, the circuit arrangement configured to initialize a redundant memory device from the plurality of memory devices with data stored in a failed memory device from the plurality of memory devices by directing any non-initialization fetch operations associated with the failed memory device to the failed memory device, directing any non-initialization store operations associated with the failed memory device to the redundant memory device, and processing an initialization operation by copying data from the failed memory device to the redundant memory device.

10. A memory controller comprising the circuit arrangement of claim 9.

11. A data processing system comprising the circuit arrangement of claim 9.

12. A program product, comprising a hardware definition program that defines the circuit arrangement of claim 9;

and a computer readable media bearing the hardware definition program, wherein the computer readable media includes at least one of a transmission type media and a recordable media.

13. A method of initializing a redundant memory device in a memory array, the method comprising:

(a) processing an initialization operation for a redundant memory device by copying data from a failed memory device to the redundant memory device;

(b) directing any non-initialization fetch operations associated with the failed memory device to the failed memory device; and

(c) directing any non-initialization store operations associated with the failed memory device to the redundant memory device.

14. The method of claim 13, wherein directing any non-initialization fetch operations associated with the failed memory device to the failed memory device and directing any non-initialization store operations associated with the failed memory device to the redundant memory device are performed during processing of the initialization operation.

15. The method of claim 13, further comprising directing any non-initialization fetch operations associated with the failed memory device to the redundant memory device after processing of the initialization operation.

16. A method of initializing a redundant memory device in a memory array, the method comprising:

(a) processing an initialization operation for a device by copying data from a failed memory device to the redundant memory device;

(b) directing any non-initialization fetch operations associated with the failed memory device to the failed memory device;

(c) directing any non-initialization store operations associated with the failed memory device to the redundant memory device; and

(d) directing any non-initialization fetch operations associated with the failed memory device to the redundant memory device after processing of the initialization operation, and wherein;

(i) the memory array includes a plurality of primary memory devices that include the failed memory device, each primary memory device including at least one data line configured to supply a primary data bit, wherein the redundant memory device includes at least one data line configured to supply a redundant data bit;

(ii) directing any non-initialization fetch operations associated with the failed memory device to the redundant memory device after processing of the initialization operation includes controlling the select inputs of a plurality of fetch multiplexers, each fetch multiplexer including the select input, first and second data inputs, and an output, the first data input coupled to receive the primary data bit from an associated primary memory device, the second data input coupled to receive the redundant data bit from the redundant memory device; and

(iii) directing any non-initialization store operations associated with the failed memory device to the redundant memory device includes controlling the select input of a store multiplexer including the select input, a plurality of data inputs, and an output, the output coupled to the data line from the redundant memory device, and the plurality of data inputs configured to receive a plurality of primary data bits forming data word to be stored in the memory array.

17. The method of claim 16, wherein:

(a) directing any non-initialization fetch operations associated with the failed memory device to the failed memory device includes driving the select input of each of the fetch multiplexers to control each fetch multiplexer to output the primary data bit from the associated primary memory device; and

(b) directing any non-initialization fetch operations associated with the failed memory device to the redundant memory device after processing of the initialization operation includes driving the select input of the fetch multiplexer associated with the failed memory device to control such fetch multiplexer to output the redundant data bit in lieu of the primary data bit associated with the failed memory device.

18. The method of claim 17, further comprising determining whether processing of the initialization operation is complete by polling an initialization indicator.

19. The method of claim 17, wherein copying data from the failed memory device to the redundant memory device includes:

(a) fetching data from the memory array;

(b) processing the fetched data using error correction code (ECC) logic to generate error corrected data; and

(c) storing the error corrected data back into the memory array.

20. A method of initializing a redundant memory device in a memory array, the method comprising:

(a) copying data from a failed memory device to a redundant memory device;

(b) receiving non-initialization store and fetch operations during the copying of data from the failed memory device to the redundant memory device;

(c) prior to completing the copying of data from the failed memory device to the redundant memory device, redirecting each received non-initialization store operation associated with the failed memory device from the failed memory device to the redundant memory device; and

(d) after completing the copying of data from the failed memory device to the redundant memory device, redirecting each received non-initialization fetch operation associated with the failed memory device from the failed memory device to the redundant memory device.

21. The method of claim 20, wherein, prior to completing the copying of data from the failed memory device to the redundant memory device, received non-initialization fetch operations associated with the failed memory device are directed to the failed memory device.