Generating an instance-based representation of a design hierarchy
First Claim
1. A method for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip, comprising:
- receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes;
wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the design hierarchy;
wherein the layout of the given node in the design hierarchy is specified by a first cell that specifies the layout of one or more nodes in the design hierarchy;
for each node within the design hierarchy, determining how interactions with the node'"'"'s siblings change the layout of the node as specified by the first cell, determining how environmental attributes specified by a parent of the node change the layout of the node as specified by the first cell, and if the changes result in a new node for which no instance has been created, creating a new instance for the node.
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Abstract
One embodiment of the invention provides a system for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip. This system operates by receiving a design hierarchy specifying the layout of the circuit, wherein the design hierarchy includes a set of hierarchically organized nodes. Within this design hierarchy, a given node specifies a geometrical feature, which can be comprised of lower-level geometrical features. These lower-level geometrical features are represented by lower-level nodes that appear under the given node in the design hierarchy. Furthermore, the layout of the given node is specified by a first cell, which in turn specifies the layout of one or more nodes in the design hierarchy. For each node within the design hierarchy, the system determines how interactions with the node'"'"'s siblings and/or parent, and possibly other surrounding geometries, change the layout of the node as specified by the first cell. If the changes result in a new node for which no instance has been created, the system creates a new instance for the node.
365 Citations
28 Claims
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1. A method for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip, comprising:
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receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes;
wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the design hierarchy;
wherein the layout of the given node in the design hierarchy is specified by a first cell that specifies the layout of one or more nodes in the design hierarchy;
for each node within the design hierarchy, determining how interactions with the node'"'"'s siblings change the layout of the node as specified by the first cell, determining how environmental attributes specified by a parent of the node change the layout of the node as specified by the first cell, and if the changes result in a new node for which no instance has been created, creating a new instance for the node. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
performing design rule checking on the layout;
performing (parasitic) extraction on the layout; and
performing optical proximity correction on the layout.
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5. The method of claim 3, wherein analyzing the layout involves partitioning the layout so that different instances can be processed by different threads executing in parallel.
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6. The method of claim 1, further comprising replacing each node in the design hierarchy with:
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a holding cell that replaces the node in the design hierarchy;
a physical cell under the holding cell that specifies environmental attributes and areas of interest for the node; and
an actual cell under the holding cell.
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7. The method of claim 1, further comprising determining whether the instance-based representation reduces an amount of layout that must be analyzed below a threshold value, and if not, using another representation of the layout instead of the instance-based representation in subsequent analysis operations.
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8. The method of claim 1, wherein the environmental attributes specified by the parent of the node include geometrical features to be added to the node and to the node'"'"'s siblings.
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9. The method of claim 1, wherein the design hierarchy is specified in GDSII format.
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10. A computer-readable storage medium storing instructions that when executed by a computer cause the computer to perform a method for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip, the method comprising:
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receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes;
wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the design hierarchy;
wherein the layout of the given node in the design hierarchy is specified by a first cell that specifies the layout of one or more nodes in the design hierarchy;
for each node within the design hierarchy, determining how interactions with the node'"'"'s siblings change the layout of the node as specified by the first cell, determining how environmental attributes specified by a parent of the node change the layout of the node as specified by the first cell, and if the changes result in a new node for which no instance has been created, creating a new instance for the node. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18)
performing design rule checking on the layout;
performing (parasitic) extraction on the layout; and
performing optical proximity correction on the layout.
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14. The computer-readable storage medium of claim 13, wherein analyzing the layout involves partitioning the layout so that different instances can be processed by different threads executing in parallel.
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15. The computer-readable storage medium of claim 10, wherein the method further comprises replacing each node in the design hierarchy with:
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a holding cell that replaces the node in the design hierarchy;
a physical cell under the holding cell that specifies environmental attributes and areas of interest for the node; and
an actual cell under the holding cell.
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16. The computer-readable storage medium of claim 10, wherein the method further comprises determining whether the instance-based representation reduces an amount of layout that must be analyzed below a threshold value, and if not, using another representation of the layout instead of the instance-based representation in subsequent analysis operations.
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17. The computer-readable storage medium of claim 10, wherein the environmental attributes specified by the parent of the node include geometrical features to be added to the node and to the node'"'"'s siblings.
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18. The computer-readable storage medium of claim 10, wherein the design hierarchy is specified in GDSII format.
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19. An apparatus that generates an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip, comprising:
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a receiving mechanism that is configured to receive a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes;
wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the design hierarchy;
wherein the layout of the given node in the design hierarchy is specified by a first cell that specifies the layout of one or more nodes in the design hierarchy;
a instance generator, wherein for each node in the design hierarchy, the instance generator is configured to;
determine how interactions with the node'"'"'s siblings change the layout of the node as specified by the first cell, determine how environmental attributes specified by a parent of the node change the layout of the node as specified by the first cell, and to create a new instance for the node if the changes result in a new node for which no instance has been created. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27)
design rule checking on the layout;
extraction (parasitic) on the layout; and
optical proximity correction on the layout.
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23. The apparatus of claim 21, wherein the analysis mechanism is additionally configured to partition the layout so that different instances can be processed by different threads executing in parallel.
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24. The apparatus of claim 19, further comprising a replacement mechanism that is configured to replace each node in the design hierarchy with:
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a holding cell that replaces the node in the design hierarchy;
a physical cell under the holding cell that specifies environmental attributes and areas of interest for the node; and
an actual cell under the holding cell.
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25. The apparatus of claim 19, further comprising a thresholding mechanism that is configured to determine whether the instance-based representation reduces an amount of layout that must be analyzed below a threshold value, and if not, to use another representation of the layout instead of the instance-based representation in subsequent analysis operations.
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26. The apparatus of claim 19, wherein the environmental attributes specified by the parent of the node include geometrical features to be added to the node and to the node'"'"'s siblings.
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27. The apparatus of claim 19, wherein the design hierarchy is specified in GDSII format.
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28. A means for generating an instance-based representation of a set of geometrical features that comprise a layout of a circuit on a semiconductor chip, comprising:
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a receiving means for receiving a design hierarchy specifying the layout of the circuit, including a set of hierarchically-organized nodes;
wherein a given node in the design hierarchy specifies a geometrical feature that is comprised of lower-level geometrical features that are represented by lower-level nodes that appear under the given node in the design hierarchy;
wherein the layout of the given node in the design hierarchy is specified by a first cell that specifies the layout of one or more nodes in the design hierarchy;
an instance generation means, wherein for each node in the design hierarchy, the instance generation means, determines how interactions with the node'"'"'s siblings change the layout of the node as specified by the first cell, determines how environmental attributes specified by a parent of the node change the layout of the node as specified by the first cell, and creates a new instance for the node, if the changes result in a new node for which no instance has been created.
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Specification