Microcomputer with multiple memories for storing data
First Claim
1. A microcomputer comprising:
- M number of memories each having an N-bit width and identical addresses for storing program data being an N×
M width word in a shared manner;
a selection circuit for selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory; and
an addressing circuit for addressing the M number of memories based on an externally supplied address signal, wherein data is sequentially written into the memory which was selectively placed in an enabled state; and
designation of an address of the M number of memories outputs addressed N bit datum from each of the M number of memories, each having an N-bit width, the outputted datum being combined to output a word having an M×
N width.
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Accused Products
Abstract
A selection circuit causes either a memory 6H or 6L to enter an enabled state according to address data A16 of address data A0-A16 when a mode signal M is 1. The selection circuit comprises OR gates (10, 12) which output different outputs. When the address data A16 is 0, a nonvolatile memory 6L enters an enabled state. Then, the memory 6L is addressed according to the address data A0-A15 so that, for example, 8-bit lower data is written therein. On the other hand, when the address data A16 is 1, a nonvolatile memory 6H becomes in an enabled state. Then, the memory 6H is addressed according to the address data A0-A15 so that, for example, 8-bit upper data is written therein. Also, when an external terminal (17) is grounded, and a mode signal become 0, the OR gates (10, 12) outputs signals 0, so that the memories 6H, 6L simultaneously become in an enabled state. When data is read from corresponding addresses of each memory, data of, for example, 16-bits is obtained.
4 Citations
20 Claims
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1. A microcomputer comprising:
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M number of memories each having an N-bit width and identical addresses for storing program data being an N×
M width word in a shared manner;
a selection circuit for selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory; and
an addressing circuit for addressing the M number of memories based on an externally supplied address signal, wherein data is sequentially written into the memory which was selectively placed in an enabled state; and
designation of an address of the M number of memories outputs addressed N bit datum from each of the M number of memories, each having an N-bit width, the outputted datum being combined to output a word having an M×
N width.- View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A microcomputer comprising:
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M number of memories each having an N-bit width and identical addresses for storing program data being an N×
M width word in a shared manner;
a selection circuit for selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory; and
an addressing circuit for addressing the M number of memories based on an externally supplied address signal, wherein data is sequentially written into the memory which was selectively placed in an enabled state; and
designation of an address of the M number of memories outputs addressed N bit datum from each of the M number of memories, each having an N-bit width, the outputted datum being combined to output a word having an M×
N width.- View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A method for writing data in a microcomputer comprising the steps of:
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providing M number of memories each having an N-bit width and identical addresses for storing program data being an N×
M width word in a shared manner;
selectively placing one memory of the M number of memories in an enabled state based on an externally supplied control signal to thereby select the memory;
addressing the M number of memories based on an externally supplied address signal;
sequentially writing data into the memory which was selectively placed in an enabled state; and
outputting addressed N bit datum from each of the M number of memories in response to designation of an address thereof, each having an N-bit width, and combining the outputted datum to output a word having an M×
N width.- View Dependent Claims (16, 17, 18, 19, 20)
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Specification