Phase interpolator device and method

• US 6,509,773 B2
• Filed: 04/30/2001
• Issued: 01/21/2003
• Est. Priority Date: 04/28/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Wakayama, Myles, Wang, Hui, Baumer, Howard A., Jiang, Xicheng, Le, Michael, Buchwald, Aaron W., Madisetti, Avanindra, Van Engelen, Jurgen
• Primary Examiner(s): Wells, Kenneth B.
• Assistant Examiner(s): COX, CASSANDRA F
• Application Number:
  US09/844,266
• Publication Number:
  US 20020039394A1
• Time in Patent Office: 631 Days
• Field of Search: 327/250, 327/248, 327/231, 327/233, 327/234, 327/235, 327/355, 327/361
• US Class Current: 327/248
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H04L 2025/03477 not time-recursive
• CPC Class Codes: H04L 2025/03617 Time recursive algorithms H04L2025/03643 takes precedence
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03885 adaptive
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0274 with Costas loop
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A high-speed serial data transceiver includes multiple receivers and transmitters for receiving and transmitting multiple analog, serial data signals at multi-gigabit-per-second data rates. Each receiver includes a timing recovery system for tracking a phase and a frequency of the serial data signal associated with the receiver. The timing recovery system includes a phase interpolator responsive to phase control signals and a set of reference signals having different predetermined phases. The phase interpolator derives a sampling signal, having an interpolated phase, to sample the serial data signal. The timing recovery system in each receiver independently phase-aligns and frequency synchronizes the sampling signal to the serial data signal associated with the receiver. A receiver can include multiple paths for sampling a received, serial data signal in accordance with multiple time-staggered sampling signals, each having an interpolated phase.

Claims

1. A phase interpolation system, comprising:

a stage controller adapted to produce a plurality of stage control signals in response to a phase control input;

a plurality of reference stages, each adapted to convert one of a plurality of reference signals into a corresponding component signal in response to a respective one of the stage control signals, wherein each of the reference signals has a distinct phase; and

wherein each of the plurality of reference stages comprises

a conversion module adapted to convert the corresponding reference signal into the corresponding component signal according to a scaling factor; and

a plurality of scaling modules coupled to the conversion module; and

a combining node adapted to combine the component signals into an output signal having an interpolated phase.

2. The phase interpolation system of claim 1, wherein the plurality of scaling modules are adapted to adjust the scaling factor in response to a value of the corresponding stage control signal.

3. The phase interpolation system of claim 2, wherein the corresponding stage control signal includes a plurality of binary control subsignals;

and

wherein each of the plurality of scaling modules is adapted to receive one of the plurality of binary control subsignals.

4. The phase interpolation system of claim 3, wherein the value of the corresponding stage control signal is the sum of the corresponding binary control signals.

5. The phase interpolation system of claim 4, wherein the scaling factor increases with the value of the corresponding stage control signal.

6. The phase interpolation system of claim 1, wherein the conversion module includes a transconductance device.

7. The phase interpolation system of claim 6, wherein the transconductance device is a field effect transistor (FET).

8. The phase interpolation system of claim 1, wherein each of the component signals has a distinct phase determined by the corresponding reference signal phase.

9. The phase interpolation system of claim 1, wherein the combining node is adapted to sum the component signals into an output signal having an interpolated phase.

10. The phase interpolation system of claim 1, wherein each of the reference stages is adapted to convert a differential reference signal into a corresponding differential component signal;

and

wherein the combining node is adapted to combine the differential component signals into a differential output signal having an interpolated phase.

11. The phase interpolation system of claim 1, wherein the plurality of reference stages includes four reference stages each adapted to convert one of four reference signals into a corresponding component signal in response to a respective one of the stage control signals, wherein the four reference signals each has one of four phases that are separated at substantially 90 degrees intervals.

12. A phase interpolation system, comprising:

a stage controller adapted to produce a plurality of stage control signals in response to a phase control input;

a plurality of reference stages, each adapted to convert one of a plurality of reference signals into a corresponding component signal in response to a respective one of the stage control signals, wherein each of the reference signals has a distinct phase; and

a combining node adapted to combine the component signals into an output signal having an interpolated phase, wherein the stage controller is a phase control signal rotator adapted to adjust the plurality stage control signals such that the output signal is phase aligned with a serial data signal.

13. A phase interpolation system, comprising:

a plurality of reference stages, each adapted to convert one of a plurality of reference signals into a corresponding component signal in response to a respective one of a plurality of stage control signals, wherein each of the reference signals has a distinct phase, and wherein each of the plurality of reference stages comprises

a conversion module adapted to convert the corresponding reference signal into the corresponding component signal according to a scaling factor, and

a plurality of scaling modules coupled to the conversion module; and

a combining node adapted to combine the component signals into an output signal having an interpolated phase.