Low distortion ECG filter

• US 6,512,944 B1
• Filed: 07/20/2000
• Issued: 01/28/2003
• Est. Priority Date: 07/20/2000
• Status: Expired due to Term

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Bange, Joseph E., Kovtun, Vladimir V., Dodson, Randall
• Primary Examiner(s): Evanisko, George R.
• Assistant Examiner(s): KHAN, OMAR A
• Application Number:
  US09/620,663
• Time in Patent Office: 922 Days
• Field of Search: 128/901, 600/508, 600/509, 600/513, 600/520
• US Class Current: 600/509
• CPC Class Codes: A61B 5/30 Input circuits therefor
• CPC Class Codes: A61B 5/308 for electrocardiography [ECG]
• CPC Class Codes: A61B 5/725 using specific filters therefor, e.g. Kalman or adaptive filters A61B5/316 take precedence
• CPC Class Codes: Y10S 128/901 Suppression of noise in electric signal

Abstract

A low pass filter especially adapted for use with ECG equipment designed to negate any noise energy that may be superimposed upon the ECG signal itself. A plurality of low-pass FIR filter stages are connected in tandem between a signal input point and a signal output point where each of the stages has a distinct cut-off frequency characteristic. A device is provided for selectively turning ones of the plurality of stages on or off.

Claims

1. Signal processing apparatus comprising:

(a) a signal source;

(b) a signal output point;

(c) a plurality of concatenated digital filter stages connected between the signal source and the signal output point, each of said filter stages including

(i) a time delay buffer having an input for receiving digital data representing sampled values of a noisy analog signal at a predetermined sampling rate and for at least temporarily storing said sampled values for predetermined time intervals, said time delay buffer providing an output;

(ii) means for deriving from the output of the time delay buffer an average-over-time noise signal component falling within a predetermined frequency band, and

(iii) means for selectively subtracting the average-over-time noise signal component from the output of the time delay buffer to remove the average-over-time noise signal component from the sampled values stored in the time delay buffer.

2. The signal processing apparatus of claim 1 wherein the means for deriving the average over-time noise signal component comprises:

(a) a high-pass filter having an input connected to receive the output of the time delay buffer and producing at an output filtered data; and

(b) a dynamic noise level calculator operative to receive the filtered data from the high-pass filter and averaging the filtered data over time.

3. The signal processing apparatus of claim 2 wherein the high-pass filter is a finite impulse response filter.

4. The signal processing apparatus of claim 3 wherein the high-pass filter has a predetermined number of taps corresponding to the delay time of the time delay buffer.

5. The signal processing apparatus of claim 2 and further including means coupled to the output of the high pass filter for setting the filtered data from the high-pass filter between upper and lower limits.

6. The signal processing apparatus of claim 1 and further including a smoothing filter connected to said signal output point of the plurality of digital filter stages.

7. The signal processing apparatus of claim 1 wherein each of said plurality of digital filter stages has a different cut-off frequency value.

8. The signal processing apparatus of claim 1 and further including a control input for predetermined ones of the plurality of concatenated digital filter stages, said control input adapted to receive a digital control signal for selectively disabling at least one of the plurality of stages.

9. The signal processing apparatus of claim 8 wherein the digital control signal is applied to the means for subtracting.

10. The signal processing apparatus of claim 1 wherein the plurality of digital filter stages are each implemented in software executable by a microcomputer.

11. The signal processing apparatus of claim 1 wherein the plurality of digital filter stages are each implemented in hardware components.

12. The apparatus of claim 1 wherein the signal source comprises digitized ECG waveforms.