I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures

CAFC
  • US 6,513,077 B2
  • Filed: 07/25/2001
  • Issued: 01/28/2003
  • Est. Priority Date: 12/20/1996
  • Status: Expired due to Term
First Claim
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1. A bus system, comprising:

  • a plurality of at least one of individual lines, buses, and subbuses within at least one of a unit including at least one of a data flow processor (DFP), a field programmable gate array (FPGA), a dynamically programmable gate array (DPGA), and a unit having a multi-dimensional programmable cell architecture, the plurality of the at least one of individual lines, buses and subbuses being bundled, wherein the plurality of the at least one individual lines, buses and subbuses at least one of combines multiple units and connects at least one of memories and peripherals, and wherein standard bus systems are used, and wherein the unit includes additional ordinary connections in a manner customary with at least one of the DFP, the FPGA and the DPGA.

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