Full flow focus exposure matrix analysis and electrical testing for new product mask evaluation

• US 6,513,151 B1
• Filed: 02/26/2001
• Issued: 01/28/2003
• Est. Priority Date: 09/14/2000
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Erhardt, Jeff, Phan, Khoi
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/794,503
• Time in Patent Office: 701 Days
• Field of Search: 716/19-21, 700/108-111, 700/117-121, 430/4-5, 378/34-35, 382/141-152
• US Class Current: 716/51
• CPC Class Codes: G03F 7/70558 Dose control, i.e. achievement of a desired dose
• CPC Class Codes: G03F 7/70625 Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
• CPC Class Codes: G03F 7/70641 Focus
• CPC Class Codes: G03F 7/7065 Defects, e.g. optical inspection of patterned layer for defects
• CPC Class Codes: G03F 7/70658 Electrical testing

Abstract

A method for new product mask evaluation is provided. Focus exposure matrices are printed at one or more layers (e.g., active gate) on full flow production wafers. The focus exposure matrices are then analyzed to produce data that facilitates detecting printed defects. The full flow production wafers are also subjected to end of line electrical testing to determine bit level errors. Print defects can be correlated with bit level errors to increase confidence in detected defects. The method includes a hierarchy of testing layers, each of which produce data that can be employed in detecting defects in a reticle and/or producing a yield analysis. The method involves scanning a reticle upon which the new product mask is etched and performing a printability simulation to determine what affect, if any, detected reticle defects will have on printing defects on a wafer. After the reticle is scanned, full flow production wafers printed from the pattern on the reticle can be scanned for defects, as can resist-on-silicon flat test wafers, where a higher signal to noise ratio facilitates detecting defects that may otherwise not be detected. The reticle scanning can include critical dimension measuring by scanning electron microscopy means and/or scatterometry means.

Claims

1. A method for new product mask evaluation, comprising:

reticle scanning;

printability simulating based, at least in part, on the reticle scanning;

printing one or more focus exposure matrices on a full flow production wafer;

defect scanning;

flat wafer monitoring;

critical dimension measuring;

full flow production wafer focus exposure matrix monitoring;

end of line electrical testing; and

defect detecting.

2. The method of claim 1, further comprising product yield analyzing.

3. The method of claim 2, wherein the reticle scanning is performed by at least one of a reticle defect inspection tool and a die-to-die inspection tool.

4. The method of claim 2, wherein the printability simulating produces a prediction yield data correlating one or more detected reticle defects to a of one or more defects being printed on a wafer, wherein the wafer is printed using the new product mask being evaluated.

5. The method of claim 2, wherein the defect scanning includes image qualifying, wherein a patterned photoresist is applied to a flat silicon wafer to produce a resist-on-silicon wafer, and wherein the resist-on-silicon wafer is inspected for defects on a die-to-die basis, wherein a resist-on-silicon signal to noise ratio is higher than a signal to noise ratio on the full flow production wafer.

6. The method of claim 5, wherein the flat wafer monitoring includes at least one of Photo Track Monitoring (PTM) and Photo Cell Monitoring (PCM).

7. The method of claim 2, wherein the critical dimension measuring is performed by scatterometry.

8. The method of claim 2, wherein the critical dimension measuring is performed by scanning electron microscopy.

9. The method of claim 2, wherein the full flow production wafer focus exposure matrix monitoring occurs on at least one of a field oxide layer, a contact layer and a gate oxide layer.

10. The method of claim 2, wherein the end of line electrical testing includes a bit level failure analysis yielding bit level data across a plurality of dies.

11. The method of claim 2, wherein the product yield analyzing comprises:

generating an actual yield data; and

correlating the actual yield data with a prediction yield data.

12. The method of claim 1, wherein the focus exposure matrix is formed from a plurality of patterns created with varying resist exposure dosages and stepper focuses.

13. A data packet adapted to be transmitted between two or more processes, the data packet containing defect analysis information and product yield information produced by a method for new product mask evaluation, comprising:

reticle scanning;

printability simulating based, at least in part, on the reticle scanning;

defect scanning;

printing one or more focus exposure matrices on a full flow production wafer;

flat wafer track monitoring;

critical dimension measuring;

full flow product focus exposure matrix monitoring;

end of line electrical testing;

defect detecting; and

product yield analyzing.

14. A system for new product mask evaluation, comprising:

a reticle scanner operably coupled to a defect analyzer;

a printability simulator operably coupled to the defect analyzer;

a defect scanner operably coupled to the defect analyzer;

a flat wafer monitor operably coupled to the defect analyzer;

a critical dimension monitor operably coupled to the defect analyzer;

a full flow product focus exposure matrix monitor operably coupled to the defect analyzer; and

an end of line electrical tester operably coupled to the defect analyzer.

15. The system of claim 14, further comprising a yield predictor operably coupled to the defect analyzer.

16. The system of claim 15, wherein the reticle scanner is at least one of a reticle defect inspection tool and a die-to-die inspection tool.

17. The system of claim 15, wherein the printability simulator is adapted to produce a prediction yield data correlating one or more scanned reticle defects to a likelihood of one or more defects being printed on a wafer, wherein the wafer is printed using the new product mask being evaluated.

18. The system of claim 15, wherein the defect scanner is adapted to perform image qualifying, wherein a patterned photoresist is applied to a flat silicon wafer to produce a resist-on-silicon wafer, and wherein the resist-on-silicon wafer is inspected for defects on a die-to-die basis, wherein a resist-on-silicon signal to noise ratio is higher than a signal to noise ratio on the full flow production wafer.

19. The system of claim 15, wherein the flat wafer monitor is at least one of a Photo Track Monitor and a Photo Cell Monitor.

20. The system of claim 15, wherein the critical dimension monitor is a scanning electron microscope system.

21. The system of claim 15, wherein the critical dimension monitor is a scatterometry system.

22. The system of claim 15, wherein the full flow product focus exposure matrix monitor is adapted to monitor one or more focus exposure matrices on at least one of a field oxide layer, a contact layer and a gate oxide layer.

23. The system of claim 22, wherein the focus exposure matrices are formed from a plurality of patterns created with varying resist exposure dosage s and stepper focuses.

24. The system of claim 15, wherein the end of line electrical tester is adapted to perform a bit level failure analysis yielding bit level data across a plurality of dies.

25. The system of claim 15, wherein the yield predictor is adapted to:

generate an actual yield data; and

correlate the actual yield data with a prediction yield data.

26. A data packet adapted to be transmitted between two or more processes, the data packet containing defect detection information and product yield information produced by a system comprising:

a defect analyzer;

a reticle scanner operably coupled to the defect analyzer;

a printability simulator operably coupled to the defect analyzer;

a defect scanner operably coupled to the defect analyzer;

a flat wafer monitor operably coupled to the defect analyzer;

a critical dimension monitor operably coupled to the defect analyzer;

a full flow product focus exposure matrix monitor operably coupled to the defect analyzer;

an end of line electrical tester operably coupled to the defect analyzer; and

a yield predictor operably coupled to the defect analyzer.

27. A method for new product mask evaluation, comprising:

processing one or more focus exposure matrices (FEMs) onto a full flow product wafer;

analyzing the FEMs;

performing end of line electrical testing of one or more integrated circuits produced from the full flow product wafer upon which the one or more FEMs were processed; and

performing a yield analysis in connection with determining an overall yield based, at least in part, on data associated with analyzing the FEMs and data associated with the end of line electrical testing of the one or more integrated circuits.