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Focal plane exposure control system for CMOS area image sensors

  • US 6,515,701 B2
  • Filed: 07/24/1997
  • Issued: 02/04/2003
  • Est. Priority Date: 07/24/1997
  • Status: Expired due to Term
First Claim
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1. A control system for controlling the exposure to incident optical radiation of an active pixel image sensing device having a plurality of image signal generating pixels arranged in horizontal rows and vertical columns to form of a two-dimensional matrix, each row and column, respectively, having a respective row and column address, wherein the pixels in each horizontal row are connected to a first common horizontal reset line and a second common horizontal select line and the pixels in each vertical column are connected to a common vertical signal line, the control system comprising:

  • a single row decoder connected to each of said horizontal reset lines for resetting image signals of the pixels of a row connected to a predetermined one of said horizontal reset lines;

    said single row decoder also connected to each of said horizontal select lines for also selecting a predetermined one of said horizontal select lines for enabling image signals from pixels in the row connected to said selected select line to be read out;

    horizontal addressing means connected to each of said vertical signal lines for selecting a predetermined one of said vertical signal lines and for reading out the signal of the pixel simultaneously selected through said horizontal select lines and said vertical signal lines;

    control means connected to said horizontal addressing means and said single row decoder for controlling said horizontal addressing means and said single row decoder so that said single row decoder selects a first one of said horizontal reset lines to reset the image signals of the pixels of that row connected to said first one of said horizontal reset lines, and thereafter selects a second one of said horizontal select lines to enable the image signals of the pixels of that row connected to said second one of said horizontal select lines to be read out, wherein said second one of said horizontal select lines is spaced apart from said first one of said horizontal reset lines by a predetermined number of horizontal select lines, and said horizontal addressing means selects in ordered sequence predetermined ones of said vertical signal lines to read out in said ordered sequence the image signals from the pixels of that row connected to said second one of said horizontal select lines, reading out in said ordered sequence the signals from the pixels simultaneously selected through said second one of said horizontal select lines and said vertical signal lines, said control means thereafter operating to control said single row decoder to alternately select succeeding predetermined ones of said horizontal reset and select lines and to control said horizontal addressing means to select predetermined ones of said vertical signal lines in said ordered sequence to read out the image signals from the pixels of the succeeding rows connected to the selected horizontal select lines, reading out in said ordered sequence the signals from the pixels simultaneously selected through said succeeding predetermined one of said horizontal select lines and said predetermined ones of said vertical signal lines;

    said control means comprising;

    a control circuit for generating row and column addresses and control signals for controlling said row decoder and said horizontal addressing means; and

    two sets of tri-state buffer amplifiers, the input of each of the sets of tri-state buffer amplifiers connected to the output of the control circuit for receiving row addresses corresponding to the horizontal lines to be reset or selected and control signals from the control circuit, and the output of each of the sets of tri-state buffer amplifiers connected to the input of the row decoder for conveying said row addresses and control signals to the row decoder, each of said tri-state buffer amplifiers capable of switching between one of two low impedance output states and a high impedance output state in response to at least one of the control signals from the control circuit;

    means for generating a first row address and a second row address and column addresses and respective control signals and conveying said first row address and at least one of said respective control signals to a first one of said set of tri-state amplifiers and conveying said second row address at least one other of said respective control signals to a second one of said set of tri-state amplifiers, said row decoder alternately receiving from the output of said first one of the sets of tri-state buffer amplifiers the first row address and the at least one respective control signal and from the output of said second one of the sets of tri-state buffer amplifiers the second row address and said at least one other respective control signal;

    means for alternately selecting one of the two tri-state amplifiers, the output of said selected amplifier being received by the decoder.

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