Active pixel image sensor with a winner-take-all mode of operation

• US 6,515,702 B1
• Filed: 07/13/1998
• Issued: 02/04/2003
• Est. Priority Date: 07/14/1997
• Status: Expired due to Term

• Current Assignee: California Institute of Technology
• Original Assignee: California Institute of Technology
• Inventors: Mead, Carver, Fossum, Eric R., Yadid-Pecht, Orly
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): Ye, Lin
• Application Number:
  US09/114,689
• Time in Patent Office: 1,667 Days
• Field of Search: 348/302, 348/308, 348/246, 348/247
• US Class Current: 348/308
• CPC Class Codes: H04N 25/00 Circuitry of solid-state image sensors [SSIS]; Control thereof
• CPC Class Codes: H04N 25/47 Image sensors with pixel address output; Event-driven image sensors; Selection of pixels to be read out based on image data
• CPC Class Codes: H04N 25/76 Addressed sensors, e.g. MOS or CMOS sensors
• CPC Class Codes: H04N 3/155 Control of the image-sensor operation, e.g. image processing within the image-sensor

Abstract

An integrated CMOS semiconductor imaging device having two modes of operation that can be performed simultaneously to produce an output image and provide information of a brightest or darkest pixel in the image.

Claims

1. A CMOS radiation-sensing device, comprising:

a substrate formed of a semiconductor material;

a detector array formed in said substrate and configured to have CMOS detector pixels to detect radiation by producing electrical signals indicating said radiation;

a readout circuit having a plurality of storage cells formed in said substrate displaced from said detector array and connected to respectively receive said electrical signals from a group of pixels in said detector array in parallel to produce an output indicative of said radiation; and

a pixel-selecting circuit formed in said substrate and configured to select a special pixel from said detector array which has a maximum pixel signal amplitude in a frame captured by said detector array,

wherein said pixel-selecting circuit comprises an array of signal-processing circuits respectively connected to receive said electrical signals from said readout circuit in parallel, a ramp generator to produce a global ramp signal to said array of signal-processing circuits, an inhibitor circuit to permit a signal-processing circuit with a largest signal to output said largest signal and to inhibits other signal-processing circuits, a memory unit storing said largest signal value and an address of a corresponding pixel which produces said largest signal, and a comparator circuit to compare an existing signal in said memory unit with largest signals selected from other groups of pixels in said detector array to select said special pixel.

2. The device as in claim 1, wherein said inhibitor circuit includes an OR logic gate.

3. The device as in claim 1, wherein said signal-processing circuit includes a daisy chain circuit to select one of at least two pixels in a selected group that have substantially the same signal amplitudes.

4. The device as in claim 3, wherein each CMOS detector pixel is an active pixel sensor.

5. The device as in claim 4, wherein each CMOS detector pixel includes a photogate.

6. The device as in claim 4, wherein each CMOS detector pixel includes a photodiode.

7. The device as in claim 4, wherein each CMOS detector pixel includes a bipolar transistor.

8. A CMOS radiation-sensing device, comprising:

a substrate formed of a semiconductor material;

a detector array formed of active sensing pixels in rows and columns on said substrate;

a readout circuit having a plurality of storage cells formed in said substrate displaced from said detector array and connected to receive pixel signals from columns of active sensing pixels in said detector array in parallel;

an array of signal-processing circuits respectively connected to said storage cells of said readout circuit in parallel to receive said pixel signals from said readout circuit;

a ramp generator on said substrate to produce a global ramp signal to said array of signal-processing circuits;

an inhibitor circuit coupled to said signal-processing circuits to permit a signal-processing circuit with a largest signal in a row of pixels to output said largest signal and to inhibits other signal-processing circuits in said row; and

a comparator circuit to compare largest signals of different rows to select a pixel with a largest pixel signal in a frame captured by said detector array.

9. A method, comprising:

selecting a row of pixels from a sensor array of pixels in rows and columns on a substrate;

outputting pixel signals from the selected row of pixels to a bank of storage calls in parallel, respectively;

comparing the pixel signals in the storage cells from the selected row in response to a ramp signal common to all pixels in the selected row;

selecting a pixel in the selected row with a largest pixel signal to output while prohibiting other pixels in the selected row from being output; and

comparing largest signals of different rows in a frame captured by the sensor array to determine a pixel with a largest pixel signal in the frame.