Channel interface and protocols for cache coherency in a scalable symmetric multiprocessor system

CAFC
  • US 6,516,442 B1
  • Filed: 03/30/1999
  • Issued: 02/04/2003
  • Est. Priority Date: 12/07/1997
  • Status: Expired due to Term
First Claim
Patent Images

1. A shared-memory multi-processor system comprising:

  • a switch fabric configured to switch packets containing data;

    a plurality of channels configured to transfer the packets;

    a plurality of switch interfaces configured to exchange the packets with the switch fabric, exchange the packets over the channels, and perform error correction of the data in the packets exchanged over the channels;

    a plurality of microprocessor interfaces configured to exchange the data with a plurality of microprocessors, exchange the packets with the switch interfaces over the channels, and perform error correction of the data in the packets exchanged over the channels; and

    a memory interface configured to exchange the data with a memory device, exchange the packets with the switch interfaces over the channels, and perform error correction of the data in the packets exchanged over the channels.

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