Method and apparatus for phase locked loop having reduced jitter and/or frequency biasing

  • US 6,526,111 B1
  • Filed: 11/23/1998
  • Issued: 02/25/2003
  • Est. Priority Date: 11/23/1998
  • Status: Expired due to Term
First Claim
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1. A phase locked loop having reduces jitter, the phase locked loop comprises:

  • a phase detection circuit operably coupled to receive a reference signal and a feedback signal, wherein the phase detection circuit produces a phase difference signal based on the reference signal and the feedback signal;

    a charge pump circuit operably coupled to receive the phase difference signal and to produce, therefrom, a representative signal, wherein the charge pump circuit includes a first current source and a second current source, wherein the first current source is dominate when the phase difference signal is in a first state and the second current source is dominate when the phase difference signal is in a second state;

    a controlled oscillator operably coupled to the charge pump circuit, wherein the controlled oscillator generates an output signal based on the representative signal, wherein the feedback signal is based on the output signal; and

    a jitter control circuit operably coupled to the first and second current sources, wherein the jitter control circuit impels currents to the first and second current sources to substantially match, and wherein the jitter control circuit comprises;

    a current mirror circuit operably coupled to mirror the current of the second current source; and

    a current matching circuit coupled in series with the current mirror circuit and operably coupled to the first current source, wherein the current matching circuit provides a current that substantially matches the current of the current mirror circuit and impels the current of the first current source to substantially match the current of the current matching circuit.

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