Semiconductor memory device

• US 6,529,439 B2
• Filed: 02/22/2001
• Issued: 03/04/2003
• Est. Priority Date: 02/24/2000
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Fujioka, Shinya, Uchida, Toshiya, Hara, Kota
• Primary Examiner(s): Ho, Hoai
• Application Number:
  US09/789,514
• Publication Number:
  US 20010017813A1
• Time in Patent Office: 740 Days
• Field of Search: 365/189.11, 365/230.06, 365/230.03, 365/189.01, 365/230.01
• US Class Current: 365/230.06
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines

Abstract

A semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers, and isolation signal generating circuits generating isolation signals that control the isolation circuits. The isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits. The sub isolation signal generating circuits generate sub isolation signals having a first potential on a high-potential side. The main isolation signal generating circuits generate main isolation signals having a second potential on the high-potential side, the second potential being lower than the first potential.

Claims

1. A semiconductor memory device comprising:

an isolation circuit for disconnecting a bit line, which is coupled to a memory cell, from a sense amplifier; and

a sub isolation signal generating circuit for outputting a sub isolation signal to control the isolation circuit, in response to a main isolation signal and an address signal,

wherein a high potential of the main isolation signal is lower than a high potential of the sub isolation signal.

2. The semiconductor memory device as claimed in claim 1, wherein the sub isolation signal generating circuit comprises:

a logic circuit that operates under a first power supply that is equal to the high potential of the main isolation signal, the logic circuit receiving the main isolation signal and the address signal; and

a level conversion circuit receiving an output signal of the logic circuit and outputting the sub isolation signal.

3. The semiconductor memory device as claimed in claim 1, wherein the sub isolation signal generating circuit comprises:

a first level conversion circuit converting a potential of the main isolation signal into the high potential of the sub isolation signal;

a second level conversion circuit converting a potential of the address signal into the high potential of the sub isolation signal; and

a logic circuit operating under a second power supply that is equal to the high potential of the sub isolation signal,

the logic circuit receiving outputs of the first and second level conversion circuits and generating the sub isolation signal to control the isolation circuit.

4. The semiconductor memory device as claimed in claim 3, wherein the sub isolation signal serves as a signal for generating a bit line precharge signal that turns ON/OFF a bit-line precharging transistor.

5. The semiconductor memory device as claimed in claim 1, further comprising a main isolation signal generating circuit for outputting the main isolation signal, wherein the main isolation signal generating circuit operates under a first power supply that is equal to the high potential of the main isolation signal.

6. The semiconductor memory device as claimed in claim 5, wherein the logic circuit includes an NOR circuit, and the level conversion circuit comprising:

an inverter inverting an output signal of the NOR circuit, the inverter operating under the first power supply that is equal to the high potential of the main isolation signal;

first and second PMOS transistors having sources connected to a power supply line via which the high potential of the sub isolation signal is supplied, and drains and gates that are cross-connected;

a first NMOS transistor having a drain connected to the drain of the first PMOS transistor, a source connected to a power supply line via which a ground potential is supplied, the first NMOS transistor being turned ON/OFF by an output signal of the NOR circuit; and

a second NMOS transistor having a drain connected to the drain of the second PMOS transistor, a source connected to the power supply line via which the ground is supplied, the second NMOS transistor being turned ON/OFF by an output signal of said inverter,

the drain of the first PMOS transistor and the drain of the first NMOS transistor being connected to form an output end of the level conversion circuit.