Method and apparatus for locking a plurality of display synchronization signals

• US 6,535,208 B1
• Filed: 09/05/2000
• Issued: 03/18/2003
• Est. Priority Date: 09/05/2000
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Liu, Zemin, Zheng, Jian-Cheng, Callway, Edward G., Saltchev, Roumen
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): NGUYEN, KIMNHUNG T
• Application Number:
  US09/654,671
• Time in Patent Office: 924 Days
• Field of Search: 345/211, 345/212, 345/213, 345/1.1, 345/2.1, 345/2.2, 345/3.2
• US Class Current: 345/213
• CPC Class Codes: G09G 5/12 Synchronisation between the display unit and other units, e.g. other display units, video-disc players
• CPC Class Codes: H04N 5/073 for mutually locking plural sources of synchronising signals, e.g. studios or relay stations
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

A method and apparatus locks a plurality of display synchronization signals, such as horizontal synchronization signals and a vertical synchronization signals, from a plurality of display output devices, such as a plurality of graphics processors. The method and apparatus digitally adjusts a vertical synchronization signal associated with a first display output device, with respect to a vertical synchronization signal associated with a second graphic output device until a crossover is detected between the first and second vertical synchronization signals. This provides a type of coarse synchronization. In response to detection of the first crossover, the method and apparatus digitally adjusts a horizontal synchronization signal associated with the first display output device with respect to a horizontal synchronization signal associated with the second display device to align the synchronization signals. The adjustment of the horizontal synchronization signals provides a fine synchronization adjustment.

Claims

1. A method for locking a plurality of display synchronization signals among at least a first and second display output device operatively coupled to a common display device comprising the steps of:

(a) digitally adjusting a first vertical synchronization signal associated with the first display output device with respect to a second vertical synchronization signal associated with the second display output device until a first crossover is detected between the first and second vertical synchronization signals; and

(b) in response to detection of the first crossover, digitally adjusting a first horizontal synchronization signal associated with the first display output device with respect to a second horizontal synchronization signal associated with the second display output device to align the synchronization signals.

2. The method of claim 1 wherein the step of digitally adjusting the first and second vertical synchronization signals includes adjusting a line width portion of at least one of the vertical synchronization signals.

3. The method of claim 1 including the step of receiving a common fixed clock reference from a fixed reference source operatively coupled to the first and second display output devices wherein each of the first and second display synchronization signals is based on the common fixed clock reference.

4. The method of claim 1 including the step of repeating steps (a) and (b) in response to detection of a change in display mode selection.

5. The method of claim 1 wherein the steps of (a) and (b) are performed without adjusting a clock reference associated with any of the first and second vertical synchronization signals and the first and second horizontal synchronization signals.

6. The method of claim 1 including the step of providing first crossover detection data representing a phase relationship between the first and second vertical synchronization signals.

7. The method of claim 1 including the step of providing second crossover detection data representing a phase relationship between the first and second horizontal synchronization signals.

8. The method of claim 1 including the step of outputting video information to the common display device from each the first and second display output devices using aligned synchronization signals obtained from performing steps (a) and (b).

9. Apparatus for locking display synchronization signals among at least a first and second display output device that are operatively coupleable to a common display device comprising:

the first display output device having at least a first display synchronization signal;

the second display output device having at least a second display synchronization signal;

a digital synchronization signal phase detection circuit operatively coupled to receive the first and second display synchronization signals operative to provide a phase relationship between the first and second synchronization signals; and

digital synchronization alignment logic operative to digitally control variation of a line width associated with the first synchronization signal to align both the first and second display synchronization signals without adjusting a clock reference associated with either of the first and second synchronization signals.

10. The apparatus of claim 9 including a common fixed clock reference source operatively coupled to the first and second display output devices wherein each of the first and second display synchronization signals is based on the common fixed clock reference.

11. The apparatus of claim 9 wherein the first synchronization signal includes a first vertical synchronization signal associated with a first display output device and wherein the second synchronization signal includes a vertical synchronization signal associated with the second display output device.

12. The apparatus of claim 9 wherein the digital synchronization signal phase detection circuit includes a crossover detection circuit operatively coupled to produce a crossover detection data in response to latching the first and second synchronization signals.

13. The apparatus of claim 11 wherein the digital synchronization signal phase detection circuit includes a first crossover detection circuit operatively responsive to the first and second vertical synchronization signals and to produce vertical sync crossover detection data, and a second crossover detection circuit operatively responsive to the first and second horizontal synchronization signals to produce horizontal sync crossover detection data.

14. The apparatus of claim 9 including a multiplexing circuit operatively coupled to selectively provide the first vertical sync signal and the first horizontal sync signal to the common display device in response to synchronizing the synchronization signals or selectively provide a second vertical synchronization signal and a second horizontal synchronization signal from the second display output device.

15. The apparatus of claim 13 wherein the vertical sync crossover detection data represents a phase relationship between the first and second vertical synchronization signals.

16. The apparatus of claim 13 wherein the horizontal crossover detection data represent a phase relationship between the first and second horizontal synchronization signals.

17. The apparatus of claim 13 wherein the digital synchronization alignment logic digitally controls variation of a line width associated with the first synchronization signal to align based on the horizontal or vertical crossover detection data.

18. The apparatus of claim 9 including a CRTC register and wherein the line width is adjusted by modifying content of the CRTC register.

19. A method for locking a plurality of display synchronization signals among at least a first and second display output device operatively coupled to a common display device comprising the steps of:

(a) digitally adjusting a first vertical synchronization signal associated with the first display output device with respect to a second vertical synchronization signal associated with the second display output device until a first crossover is detected between the first and second vertical synchronization signals by adjusting a line width portion of at least one of the vertical synchronization signals; and

(b) in response to detection of the first crossover, digitally adjusting a first horizontal synchronization signal associated with the first display output device with respect to a second horizontal synchronization signal associated with the second display output device to align the synchronization signals.

20. The method of claim 19 including the step of receiving a common fixed clock reference from a fixed reference source operatively coupled to the first and second display output devices wherein each of the first and second display synchronization signals is based on the common fixed clock reference.

21. The method of claim 20 including the step of repeating steps (a) and (b) in response to detection of a change in display mode selection.

22. The method of claim 19 wherein the steps of (a) and (b) are performed without adjusting a clock reference associated with any of the first and second vertical synchronization signals and the first and second horizontal synchronization signals.

23. The method of claim 22 including the step of providing first crossover detection data representing a phase relationship between the first and second vertical synchronization signals.

24. The method of claim 23 including the step of providing second crossover detection data representing a phase relationship between the first and second horizontal synchronization signals.

25. The method of claim 24 including the step of outputting video information to the common display device from each the first and second display output devices using aligned synchronization signals obtained from performing steps (a) and (b).