Active pixel sensor with capacitorless correlated double sampling

• US 6,535,247 B1
• Filed: 05/19/1998
• Issued: 03/18/2003
• Est. Priority Date: 05/19/1998
• Status: Expired due to Fees

• Current Assignee: RE Secured Networks LLC
• Original Assignee: Pictos Technologies Inc. (f/k/a Imperium IP Holdings (Cayman), Ltd.) (Imperium (IP) Holdings Incorporated)
• Inventors: Kozlowski, Lester J., Standley, David L.
• Primary Examiner(s): Garber, Wendy R.
• Assistant Examiner(s): WHIPKEY, JASON T
• Application Number:
  US09/081,541
• Time in Patent Office: 1,764 Days
• Field of Search: 348/241, 348/302, 348/308, 257/291, 257/292
• US Class Current: 348/241
• CPC Class Codes: H04N 25/65 applied to reset noise, e.g. KTC noise related to CMOS structures by techniques other than CDS
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components

Abstract

An imager pixel including a photodetector, a first MOS transistor functioning as the driver of a source follower amplifier, a second MOS transistor functioning as a pixel readout transistor, and a third transistor performing a dual function to reset the photodetector during a first time interval and cancel reset noise by serving as a weak current source during a second time interval.

Claims

1. An apparatus comprising:

a pixel comprising;

(a) a photodetector element having a node;

(b) a first transistor having a control leg connected to said node and second and third legs, the third leg being connected to a power supply voltage;

(c) a second transistor having a control leg and fourth and fifth legs, the fourth leg connected to the second leg of said first transistor;

(d) a third transistor having a control leg and sixth and seventh legs, the seventh leg being connected to a reset voltage source; and

a feedback loop including a waveform generator for supplying a reset voltage waveform to the control leg of said third transistor to reset said photodetector, said reset voltage waveform comprising a ground voltage level followed by a first reset voltage pulse for resetting the photodetector followed by an offset cancellation voltage pulse of a duration selected to cancel reset noise generated by resetting said photodetector.

2. The apparatus of claim 1 wherein said feedback loop further comprises:

a comparator circuit connected to compare the voltage on the fifth leg of said second transistor to a dark signal reference voltage.

3. The apparatus of claim 2 wherein each of said first, second and third transistors comprises a MOSFET.

4. The apparatus of claim 3 wherein each said MOSFET is fabricated in CMOS.

5. The apparatus of claim 4 wherein said photodetector comprises a substrate diode with a silicide portion thereof removed.

6. The apparatus of claim 4 wherein said photodetector comprises an n on p photodiode junction in a p-type substrate.

22. The apparatus of claim 4 wherein said photodetector comprises a p on n photodiode junction in an n-type substrate.

7. In an active pixel circuit including a photodetector, a source follower driver MOS transistor, a row select MOS transistor and a reset MOS transistor, the method comprising:

reading out the voltage on the photodetector;

resetting the photodetector; and

canceling reset noise created by resetting the photodetector by causing said reset MOS transistor to act as a current source.

8. The method of claim 7 wherein the step of reading out the voltage on the photodetector includes the step of holding off the reset MOS transistor and turning on the row select MOS transistor.

9. The method of claim 8 wherein said step of resetting the photodetector comprises the step of fully enabling said reset MOS transistor.

10. The method of claim 7 wherein said step of canceling said reset noise comprises the step of applying a selected voltage level to a gate of said reset MOS transistor.

11. The method of claim 9 wherein said step of canceling said reset noise comprises the step of applying a selected voltage level to a gate of said reset MOS transistor.

12. The method of claim 10 wherein said voltage level is selected to provide subthreshold biasing of said reset transistor.

13. The method of claim 10 wherein said voltage level is selected to cause said reset MOS transistor to act as a weak source of minority carriers.

14. The method of claim 10 wherein said voltage level is selected to last for a period of time determined by comparing the pixel signal on a leg of the row select transistor to a dark signal reference voltage.

15. The method of claim 7 wherein the step of canceling said reset noise includes the step of comparing a pixel signal on a leg of the row select transistor to a dark signal reference voltage.

16. The method of claim 7 wherein minority carriers are used to cancel said reset noise.

17. The method of claim 16 wherein the offset nulling minority carriers are either holes or electrons.

18. An imager pixel comprising:

a first transistor means for functioning as the driver of a source follower amplifier during signal readout;

second transistor means for controlling signal readout; and

third transistor means for serving as a reset switch during a first time interval and as a weak current source during a second time interval.

19. An apparatus comprising a plurality of the pixels of claim 18 and further comprising on-chip digital logic means for reading the signal from each pixel, multiplexing the signal outputs from an array of pixels, and enabling completion of a feedback loop for controlling the length of said second time interval.

20. The apparatus of claim 19 wherein said multiplexing is performed by horizontal and vertical shift registers.

21. An apparatus comprising a plurality of the pixels of claim 18 and further comprising column buffer means for providing an independent feedback loop to cancel each pixel'"'"'s reset noise by biasing the third transistor means to act as a current source and thereby provide the necessary number of minority carriers to cancel the reset noise.

23. An apparatus comprising:

a pixel comprising;

(a) a photodetector element having a node;

(b) a first transistor having a control leg connected to said node and second and third legs, the third leg being connected to a power supply voltage;

(c) a second transistor having a control leg and fourth and fifth legs, the fourth leg connected to the second leg of said first transistor;

(d) a third transistor having a control leg and sixth and seventh legs, the seventh leg being connected to a reset voltage source; and

means for supplying a reset voltage waveform to the control leg of said third transistor to reset said photodetector, said reset voltage waveform comprising a ground voltage level followed by a first reset voltage pulse for resetting the photodetector followed by an offset cancellation voltage pulse of a duration selected to cancel reset noise generated by resetting said photodetector.

24. The apparatus of claim 23 wherein said means for supplying further comprises:

comparator circuit connected to compare the voltage on the fifth leg of said second transistor to a dark signal reference voltage.

25. The apparatus of claim 24 wherein each of said first, second and third transistors comprises a MOSFET.