Semiconductor memory device

• US 6,535,456 B2
• Filed: 03/11/2002
• Issued: 03/18/2003
• Est. Priority Date: 10/15/1990
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Toda, Haruki, Saito, Shozo, Tokushige, Kaoru
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/093,935
• Publication Number:
  US 20020093873A1
• Time in Patent Office: 372 Days
• Field of Search: 365/230.01, 365/230.03, 365/230.06, 365/236, 365/191, 365/233
• US Class Current: 365/233.5
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1036 using data shift registers
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management

Abstract

A semiconductor device includes a memory cell array, a counting section, a control section, a specification section and a data input/output section. The counting section configured to count transition of the clock signal and determine first data of a plurality of data to be transferred sequentially. The control section configured to fetch information indicating a memory cell location in the memory cell array in response to a counting result of the counting section and control consecutive input and output of a plurality of data stored in the memory cell array every cycle of the clock signal. The specification section configured to decode the information fetched by the control section and designate a memory cell in the memory cell array. The data input/output section configured to input data to or output data from the memory cell designated by the specification section, wherein input and output of the data are time-shared.

Claims

1. A semiconductor device comprising:

a memory cell array having a plurality of memory cells arranged in rows and columns;

a counting section, to which a clock signal is input, configured to count transitions of the clock signal and to determine first data of a plurality of data to be transferred sequentially;

a control section configured to fetch information indicating a memory cell location in the memory cell array in response to a counting result of said counting section and to control consecutive input and output of a plurality of data stored in the memory cell array each cycle of the clock signal;

a specification section configured to decode the information fetched by said control section and to designate a memory cell in the memory cell array; and

a data input/output section configured to input data to the memory cell designated by said specification section and to output data from the memory cell designated by said specification section, wherein input and output of the data are time-shared.

2. A semiconductor device according to claim 1, wherein said information indicating the memory cell location in the memory cell array includes address signals, and said address signals are fetched without being divided into rows and columns.

3. A semiconductor device according to claim 1, wherein said control section operates in response to a first signal that determines whether data are read or written, and a second signal that determines whether the first signal is latched or not, and

data from said date input/output section are input to and output from the memory cell designated by the specification section independently of a timing at which the information indicating the memory cell location in the memory cell array is fetched.

4. A semiconductor device according to claim 3, wherein data from said data input/output section are input to and output from the memory cell designated by the specification section following a predetermined number of cycles of said clock signal after latching of the first signal is instructed by said second signal.

5. A semiconductor device according to claim 1, wherein said data input/output section is switched between a state of outputting the data and a high-impedance state in response to an output enable signal.