Shared memory based network switch and the network constructed with the same

• US 6,535,516 B1
• Filed: 07/09/1999
• Issued: 03/18/2003
• Est. Priority Date: 12/10/1998
• Status: Expired due to Term

• Current Assignee: A10 Networks Incorporated
• Original Assignee: Industrial Technology Research Institute
• Inventors: Fan, Kuo-Yen, Leu, Kuo-Cheng, Wang, Shu-Wei, Huang, Hai-Yang
• Primary Examiner(s): Olms, Douglas
• Assistant Examiner(s): Sam, Phirin
• Application Number:
  US09/350,471
• Time in Patent Office: 1,348 Days
• Field of Search: 370/428, 370/351, 370/352, 370/353, 370/354, 370/386, 370/389, 370/392, 370/396, 370/395.31, 370/399, 370/395.4, 370/395.72, 370/395.71, 370/400, 370/401, 370/402, 370/403, 370/404, 370/405, 370/409, 370/412, 370/413, 370/415, 370/417, 370/462, 365/189.04, 365/230.01, 365/230.05
• US Class Current: 370/395.72
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 49/90 Buffering arrangements

Abstract

A shared memory based network having a transferring network switch and a receiving network switch. In this network, each network switch has a stack, queues corresponding to output ports and a dared control port. The stack stores available buffer addresses of the shared memory. Each of the queues stores to-be-accessed buffer addresses of the corresponding output port. The shared control port is driven to indicate states of the shared memory based network, so that th stack of the transferring network switch is identical with the stack of the receiving network switch. The shared memory can be read by all output ports of both the transferring network switch and the receiving network switch according to their corresponding queues.

Claims

1. A shared memory based network comprising a transferring network switch and a receiving network switch, each network switch having a stack, a plurality of queues corresponding to a plurality of output ports, and a shared control port, the stack storing available buffer addresses of the shared memory, each of the queues storing to-be-accessed buffer addresses of the corresponding output port, the share control port driven to indicate states of the shared memory based network so that the stack of the transferring network switch is identical with the stack of the receiving network switch and the shared memory being read by the output ports of both the transferring network switch and the receiving network switch according to the corresponding queues.

2. The shared memory based network as claimed in claim 1, wherein the shared control port has a synchronization signal to define exchanging cycles for the output ports of both the transferring network switch and the receiving network switch.

3. The shared memory based network as claimed in claim 2, wherein the exchanging cycles are obtained by time-division multiplexing (TDM) using the synchronization signal.

4. The shared memory based network as claimed in claim 1, further including a multicast count for each buffer to indicate the number of times the buffer is to be accessed.

5. A shared memory based network switch connecting to shared memory through a shared bus, the shared memory having a plurality of buffers, the network switch comprising:

a stack storing available buffer addresses of the shared memory;

a plurality of queues corresponding to a plurality of output ports, each of the queues storing to-be-accessed buffer addresses of the corresponding output port, each output port reading the shared memory according to the port'"'"'s corresponding queue; and

a shared control port driven to various states so thy the stack pops out or pushes in a top buffer address.

6. The shared memory based network switch as claimed in claim 5, wherein the shared control port has a synchronization signal to define exchanging cycles for all the output ports.

7. The shared memory based network switch as claimed in claim 6, wherein the exchanging cycles for all the output ports are obtained by time-division multiplexing (TDM) using the synchronization signal.

8. The shared memory based network switch as claimed in claim 5, further including a multicast count for each buffer indicate the number of times the buffer is to be accessed.

9. The shared memory based network switch as claimed in claim 5, wherein the stack is structured as a first-in-first-out memory.

10. The shared memory based network switch as claimed in claim 5, wherein the stack is structured as a dynamically linked memory.