Satellite payload processing system using polyphase demultiplexing, quadrature phase shift keying demodulation and rate alignment

• US 6,542,480 B1
• Filed: 03/09/1999
• Issued: 04/01/2003
• Est. Priority Date: 11/05/1996
• Status: Expired due to Fees

• Current Assignee: WorldSpace, Inc.
• Original Assignee: WorldSpace, Inc.
• Inventors: Campanella, S. Joseph
• Primary Examiner(s): Bost, Dwayne
• Assistant Examiner(s): CONTEE, JOY KIMBERLY
• Application Number:
  US09/265,537
• Time in Patent Office: 1,484 Days
• Field of Search: 370/321, 370/322, 370/323, 370/324, 370/203, 370/206, 370/210, 370/215, 370/465, 370/480, 370/467, 370/481, 370/506, 370/514, 375/211, 375/214, 375/271, 375/279, 375/280, 375/283, 375/308, 375/309, 375/330
• US Class Current: 370/324
• CPC Class Codes: H04B 7/18515 Transmission equipment in satellites or space-based relays

Abstract

A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers comprises a polyphase demultiplexer processor for separating the uplink signal into a time division multiplexed data stream of symbols. The polyphase demultiplexer processor presents the symbols corresponding to each of a plurality of carriers at respective ones of the frequencies in the uplink signal sequentially to an output of the polyphase demultiplexer processor. A phase shift keying demodulator and differential decoder demodulates the stream of symbols into corresponding time division multiplexed stream of digital baseband bits, which are then rate-aligned with respect to an on-board clock.

Claims

1. A satellite payload processing system for processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers and having an on-board clock, comprising:

a polyphase demultiplexer processor for separating said uplink signal into a time division multiplexed data stream of symbols and presenting said symbols corresponding to each of said plurality of carriers at respective ones of said frequencies in said uplink signal sequentially to an output of said polyphase demultiplexer processor;

a phase shift keying demodulator connected to said output of said polyphase demultiplexer processor for demodulating said stream of symbols into corresponding time division multiplexed stream of digital baseband bits; and

a rate alignment device for processing said time division multiplexed stream of digital baseband bits to compensate for rate differences between said on-board clock and said symbols corresponding to each of said plurality of carriers received at said satellite, and for demultiplexing said time division multiplexed stream into parallel, rate-aligned channels.

2. A satellite payload processing system as claimed in claim 1, further comprising a differential decoder connected to said phase shift keying demodulator for recovering said stream of symbols when said stream of symbols is differentially encoded for said uplink carrier signal.

3. A satellite payload processing system as claimed in claim 1, wherein said phase shift keying demodulator is a quadrature phase shift keying demodulator for demodulating each of said symbols into two corresponding bits.

4. A satellite payload processing system as claimed in claim 1, further comprising a switching and routing processor for routing said channels into at least one of a plurality of time division multiplexed downlink carriers.

5. A satellite payload processing system as claimed in claim 1, wherein uplink signal comprises frames and each of said frames comprises a header having bits, said rate alignment device being operable to perform a rate alignment operation selected from the group consisting of adding at least one bit of predetermined value to said header, removing at least one of said bits and allowing the number of said bits in said header to remain unchanged, said rate alignment selecting which said rate alignment operation from said group to implement in accordance with whether timing of said symbols is determined, respectively, to be lagging behind said on-board clock, to be leading said on-board clock, or synchronized with said on-board clock.

6. A method of processing an uplink signal consisting of a plurality of single-channel-per-carrier, frequency division multiple access carriers at a satellite having an on-board clock, comprising the steps of:

separating said uplink signal into a time division multiplexed data stream of symbols and presenting said symbols corresponding to each of said plurality of carriers as respective ones of said frequencies in said uplink signal sequentially for demodulation;

demodulating said stream of symbols into corresponding time division multiplexed stream of digital baseband bits;

compensating for rate differences between said on-board clock and said symbols corresponding to each of said plurality of carriers received at said satellite; and

demultiplexing said time division multiplexed stream into parallel, rate-aligned channels.

7. A method as claimed in claim 6, wherein an uplink signal comprises frames and each of said frames comprises a header having bits, and said compensating step comprises the steps of:

determining the timing of said symbols to be characterized as one of lagging behind said on-board clock, leading said on-board clock, and synchronized with respect to said on-board clock; and

performing a respective one of a plurality of rate alignment operations comprising adding at least one bit of predetermined value to said header, removing at least one of said bits and allowing the number of said bits in said header to remain unchanged.