Method and apparatus of testing memory device power and ground pins in an array assembly platform

• US 6,545,497 B2
• Filed: 03/15/2001
• Issued: 04/08/2003
• Est. Priority Date: 03/15/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Reichle, Dave, Chadwick, Gary, Remmerden, Dave, Hebert, Dave
• Primary Examiner(s): Cuneo, Kamand
• Assistant Examiner(s): Nguyen, Tung X.
• Application Number:
  US09/809,727
• Publication Number:
  US 20020132382A1
• Time in Patent Office: 754 Days
• Field of Search: 324/765, 324/761, 324/763, 324/764, 324/158.1
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester

Abstract

An apparatus and technique for performing continuity tests of power and ground pins on a packaged integrated circuit. The technique includes using a first and second fanout circuit each including a number of signal paths. Each signal path includes a switch and corresponds to a power or ground socket on a board configured to hold a number of integrated circuit packages. The fanout circuits allow full device testing, as well as testing of individual pins. By controlling the state of the switches, power and ground may be selectively supplied to power and ground pins to check the continuity of the signals from the integrated circuit device within the package to the external pins provided to route the signal to an external device.

Claims

1. A method of testing power pins in an electronic device comprising the acts of:

(a) inserting a semiconductor device into a test socket, the semiconductor device having a plurality of power pins;

(b) providing a power signal to a fanout circuit, the fanout circuit comprising a plurality of switches and configured to receive a power signal and produce a plurality of outputs, each output providing the power signal to a respective one of the plurality of power pins on the electronic device through one of the plurality of switches when the one switch is in a first state;

(c) placing a first of the plurality of switches in the fanout circuit in a first state;

(d) placing the remaining of the plurality of switches in a second state; and

(e) reading a voltage at each of the power pins.

2. The method of testing power pins in an electronic device, as set forth in claim 1, wherein the electronic device comprises a memory device.

3. The method of testing power pins in an electronic device, as set forth in claim 1, wherein the electronic device comprises a semiconductor device.

4. The method of testing power pins in an electronic device, as set forth in claim 1, comprising the act of performing parametric tests without removing the semiconductor device from the test socket.

5. The method of testing power pins in an electronic device, as set forth in claim 1, wherein act (c) comprises the act of placing the first of the plurality of switches in the fanout circuit in a closed state.

6. The method of testing power pins in an electronic device, as set forth in claim 1, wherein acts (a) through (e) are performed in the recited order.

7. A method of testing ground pins in an electronic device comprising the acts of:

(a) inserting a semiconductor device into a test socket, the semiconductor device having a plurality of ground pins;

(b) providing a ground signal to a fanout circuit, the fanout circuit comprising a plurality of switches and configured to receive a ground signal and produce a plurality of outputs, each output providing the ground signal to a respective one of the plurality of ground pins on the semiconductor device through one of the plurality of switches when the switch is in a first state;

(c) placing a first of the plurality of switches in the fanout circuit in a first state;

(d) placing the remaining of the plurality of switches in a second state; and

(e) reading a voltage at each of the ground pins.

8. The method of testing ground pins in an electronic device, as set forth in claim 7, wherein the electronic device comprises a memory device.

9. The method of testing ground pins in an electronic device, as set forth in claim 7, wherein the electronic device comprises a semiconductor device.

10. The method of testing ground pins in an electronic device, as set forth in claim 7, comprising the act of performing parametric tests without removing the semiconductor device from the test socket.

11. The method of testing ground pins in an electronic device, as set forth in claim 7, wherein act (c) comprises the act of placing the first of the plurality of switches in the fanout circuit in a closed state.

12. The method of testing ground pins in an electronic device, as set forth in claim 10, wherein acts (a) through (e) are performed in the recited order.

13. A method of verifying the continuity of a plurality of pins on an electronic package inserted in a test socket, the pins comprising a plurality of power pins and a plurality of ground pins, the method comprising the acts of:

(a) enabling a power signal to only one of the plurality of power pins;

(b) measuring a voltage on each of the plurality of power pins;

(c) enabling a ground signal to only one of the plurality of ground pins; and

(d) measuring a voltage on each of the plurality of ground pins.

14. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, wherein the electronic package comprises a memory device.

15. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, wherein the electronic package comprises a semiconductor device.

16. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, comprising the act of performing parametric tests without removing the semiconductor device from the test socket.

17. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, wherein act (a) comprises the act of enabling the power signal to only one of the plurality of power pins by closing a first switch.

18. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, wherein act (c) comprises the act of enabling the ground signal to only one of the plurality of ground pins by closing a second switch.

19. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, comprising the act of driving all but the one of the plurality of power pins to a logical low through a plurality of pull-down resistors, each of the plurality of pull-down resistors corresponding to one of the plurality of power pins.

20. The method of verifying the continuity of a plurality of pins on an electronic package, as set forth in claim 13, comprising the act of driving all but the one of the plurality of ground pins to a logical high through a plurality of pull-up resistors, each of the plurality of pull-up resistors corresponding to one of the plurality of ground pins.

21. The method of testing power pins in an electronic device, as set forth in claim 13, wherein acts (a) through (d) are performed in the recited order.

27. The apparatus for testing power and ground pins on an electronic, as set forth in claim 21, wherein each of the second nodes of each of the plurality of switches in the second fanout circuit is coupled to a power signal through a resistor.

22. An apparatus for testing power and ground pins on an electronic package, the apparatus comprising:

a socket board configured to couple a plurality of electronic packages to power source and a ground source, the electronic packages each comprising a plurality of power and ground pins;

a first fanout circuit comprising a plurality of switches, each of the plurality of switches, having a first node and a second node and providing an electrical path from the power source to a respective one of the plurality of power pins;

a second fanout circuit comprising a plurality of switches, each of the plurality of switches having a first node and a second node and providing an electrical path from the ground source to each of the plurality of ground pins; and

a control circuit configured to control each of the switches in the first fanout circuit and the second fanout circuit.

23. The apparatus for testing power and ground pins on an electronic package, as set forth in claim 22, wherein the socket board comprises a plurality of sockets configured to receive a plurality of electronic packages.

24. The apparatus for testing power and ground pins on an electronic package, as set forth in claim 22, wherein the electronic package comprises a memory package.

25. The apparatus for testing power and ground pins on an electronic package, as set forth in claim 22, wherein the electronic package comprises a semiconductor package.

26. The apparatus for testing power and ground pins on an electronic package, as set forth in claim 22, wherein each of the second nodes of each of the plurality of switches in the first fanout circuit is coupled to a ground signal through a resistor.

28. The apparatus for testing power and ground pins on an electronic, as set forth in claim 22, wherein the control circuit is configured to read a voltage measurement at each of the plurality of power and ground pins.

33. The test apparatus, as set forth in claim 28, comprising a plurality of resistors, each of the plurality of resistors being coupled between each of the plurality of switches and one of a power source and a ground source.

29. A test apparatus comprising:

a test socket configured to couple an electronic device to a printed circuit board and to provide an electrical path for both parametric testing and power/ground verification;

a plurality of switches configured to transmit signals when the switches are in a first state;

a plurality of conductive traces coupled between each of the plurality of switches and the test socket; and

a control device configured to provide control of the plurality of switches.

30. The test apparatus, as set forth in claim 29, wherein the test apparatus is configured to perform both parametric testing and power pin verification testing without removing the electronic device from the test socket.

31. The test apparatus, as set forth in claim 29, wherein the electronic device comprises a memory device.

32. The test apparatus, as set forth in claim 29, wherein the electronic device comprises a semiconductor device.