Single substrate camera device with CMOS image sensor
DCFirst Claim
Patent Images
1. A single chip camera device, comprising:
- a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and further comprising double sampling charge storage elements on said substrate.
2 Assignments
Litigations
0 Petitions
Accused Products
Abstract
Single substrate device is formed to have an image acquisition device and a controller. The controller on the substrate controls the system operation.
140 Citations
66 Claims
-
1. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and further comprising double sampling charge storage elements on said substrate. - View Dependent Claims (2)
-
-
3. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said array of photoreceptors are controlled to output an entire row of said photoreceptors substantially simultaneously; and
a plurality of double sampling charge storage elements integrated on said substrate;
one for each of said columns.- View Dependent Claims (4)
-
-
5. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of active pixel type photoreceptors, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired colum for read out, and a row selector which allows selection of a desired row fro readout. - View Dependent Claims (6)
-
-
7. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout, wherein said row selector includes a latch element, storing a value for a row to be selected, and a counter, allowing incrementing of said value to read a next consecutive row, said latch element and said counter both being integrated on said substrate.
-
-
8. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreeptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said signal controlling device includes a column selector allowing selection of a desired column for read out, and a row selector which allows selection of a desired row for readout, wherein said colum selector includes presettable start and stop column decoder counters, which are preset to start and stop at any desired value. - View Dependent Claims (9)
-
-
10. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a mode selector device, selecting a mode of operation of said chip, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and second mode of operation, different that said first mode of operation, for operation with photodiodes. - View Dependent Claims (11)
-
-
12. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and further comprising a correlated double sampling circuit.
-
-
13. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit controls readout from said chip in a correlated double sampling mode.
-
-
14. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that a least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors.
-
-
15. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and further comprising fixed pattern noise reduction circuits, on said substrate.
-
-
16. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a noise reduction circuit, wherein said timing circuit times an operation of said noise reduction circuit to occur during a time of the video signal which is not being displayed.
-
-
17. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that a least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit.
-
-
18. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, in a way such that at least a plurality of said photoreceptors output their signals at substantially the same time, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, further comprising a mode selector device, selecting a mode of operation of said chip, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and second mode of operation, different that said first mode of operation, for operation with photodiodes.
-
-
19. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing present of at least one of a start address for output or a stop address for output;
said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28)
-
-
29. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said array of photoreceptors includes an active pixel sensor, where each element of the array includes both a photoreceptor and a readout amplifier integrated within the same substrate as the photoreceptor. - View Dependent Claims (30)
-
-
31. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit.
-
-
32. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, and a noise reduction circuit. - View Dependent Claims (33)
-
-
34. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors in a first mode or in a second mode, depending on a type of photoreceptor being used. - View Dependent Claims (35, 36, 37, 38, 39, 40, 41)
-
-
42. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors in a first mode or in a second mode, depending on a type of photoreceptor being used, further comprising a noise reduction circuit.
-
-
43. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, said control portion including common logic elements to control row and address decoders and delay counters. - View Dependent Claims (44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58)
-
-
59. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, said control portion including common logic elements to control row and address decoders and delay counters, further comprising a mode selector device, selecting a mode of operation of said chip. - View Dependent Claims (60, 61)
-
-
62. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors.
-
-
63. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in row and columns;
a charge storage element, associated with each said columns;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;
said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously, further comprising a mode selector device, selecting a mode of operation of said chip.
-
-
64. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors arranged in rows and columns;
a charge storage element, associated with each said colum;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, said control portion including common logic elements to control all pixels on a selected row to sample said all pixels onto said charge storage elements substantially simultaneously, wherein said photoreceptors are either photogates or photodiodes, and said mode selector device selects a first mode of operation for operation with photogates, and a second mode of operation, different than said first mode of operation, for operation with photodiodes.
-
-
65. A single chip camera device, comprising:
-
a substrate, having integrated thereon an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS;
said image acquisition portion integrated in said substrate including an array of photoreceptors;
said control portion integrated in said substrate including a signal controlling device, controlling said photoreceptors to output their signals, and including a preset buffer, allowing preset of at least one of a start address for output or a stop address for output;
said control portion also including, integrated in said substrate, a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors, wherein said timing circuit allows changing an integration time for said array of photoreceptors.
-
-
66. A method of controlling a single chip camera, comprising:
-
integrating, on a single substrate, an image acquisition portion and a control portion, both of which are formed using a logic family that is compatible with CMOS, said image acquisition portion integrated in said substrate including an array of photoreceptors, and a signal controlling device, controlling said photoreceptors and a timing circuit integrated within the same substrate that houses the array of photoreceptors, controlling a timing of operation of said array of photoreceptors;
determining a first mode of operation for said photoreceptors being photogates, and a second mode of operation for said photoreceptors being photodiodes;
using said on-chip timing and control circuit to control sequences for accessing rows in a specified order depending on said mode of operation, using a first sequence for said first mode of operation for photogates, and a second mode of operation for said second mode for photodiodes, a timing for said first mode being different than a timing for said second mode.
-
Specification